Merge branch 'master' of github.com:steveicarus/iverilog
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commit
e1c0fa5feb
2
parse.y
2
parse.y
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@ -3041,7 +3041,7 @@ module_item
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current_function = 0;
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delete[]$4;
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if ($7==0 && !gn_system_verilog()) {
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yyerror(@7, "error: Empty parenthesis syntax requires SystemVerilog.");
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yyerror(@4, "error: Empty parenthesis syntax requires SystemVerilog.");
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}
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}
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| K_function automatic_opt function_range_or_type_opt IDENTIFIER error K_endfunction
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