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vhdlpp: "resize" function.

This commit is contained in:
Maciej Suminski 2015-03-02 16:35:51 +01:00
parent e33b8b4dde
commit 1de3fb1625
1 changed files with 4 additions and 3 deletions
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7
vhdlpp/expression_emit.cc
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@ -560,12 +560,13 @@ int ExpFunc::emit(ostream&out, Entity*ent, ScopeBase*scope)
{
int errors = 0;
// SystemVerilog takes care of signs, depending on the lvalue
if (name_ == "to_integer" && argv_.size()==1) {
// SystemVerilog takes care of sign & width, depending on the lvalue type
if ((name_ == "to_integer" && argv_.size() == 1) ||
(name_ == "resize" && argv_.size() == 2)) {
errors += argv_[0]->emit(out, ent, scope);
}
else if (name_ == "unsigned" && argv_.size()==1) {
else if (name_ == "unsigned" && argv_.size() == 1) {
// Handle the special case that this is a cast to
// unsigned. This function is brought in as part of the
// std numeric library, but we interpret it as the same