luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add missing file/line information to a few expressions.

This commit is contained in:
Cary R 2013-06-26 21:24:19 -07:00
parent fa9a439bf1
commit 4dbd0442aa
3 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
elab_expr.cc
View File

@ -3798,6 +3798,7 @@ NetExpr* PEIdent::elaborate_expr_net_word_(Design*des, NetScope*scope,
xxx->set_line(*this);
return xxx;
}
canon_index->set_line(*this);
NetESignal*res = new NetESignal(net, canon_index);
res->set_line(*this);

1
elab_lval.cc
View File

@ -422,6 +422,7 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
// Ensure invalid array accesses are ignored.
if (canon_index == 0)
canon_index = new NetEConst(verinum(verinum::Vx));
canon_index->set_line(*this);
NetAssign_*lv = new NetAssign_(reg);
lv->set_word(canon_index);

2
elaborate.cc
View File

@ -4047,6 +4047,7 @@ NetProc* PEventStatement::elaborate_wait(Design*des, NetScope*scope,
if (expr->expr_width() > 1) {
assert(expr->expr_width() > 1);
NetEUReduce*cmp = new NetEUReduce('|', expr);
cmp->set_line(*pe);
expr = cmp;
}
@ -4094,6 +4095,7 @@ NetProc* PEventStatement::elaborate_wait(Design*des, NetScope*scope,
wait. */
assert(expr->expr_width() == 1);
expr = new NetEBComp('N', expr, new NetEConst(verinum(verinum::V1)));
expr->set_line(*pe);
eval_expr(expr);
NetEvent*wait_event = new NetEvent(scope->local_symbol());