luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vhdlpp: std_logic_vector, signed & unsigned are considered global types.

This commit is contained in:
Maciej Suminski 2015-02-16 17:53:18 +01:00
parent 0046e9eca0
commit ee840391d6
2 changed files with 3 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
vhdlpp/library.cc
View File

@ -417,10 +417,13 @@ bool is_global_type(perm_string name)
if (name == "integer") return true;
if (name == "real") return true;
if (name == "std_logic") return true;
if (name == "std_logic_vector") return true;
if (name == "character") return true;
if (name == "bit_vector") return true;
if (name == "string") return true;
if (name == "natural") return true;
if (name == "signed") return true;
if (name == "unsigned") return true;
return false;
}

8
vhdlpp/package.cc
View File

@ -73,12 +73,6 @@ void Package::write_to_stream(ostream&fd) const
// Do not include global types in types dump
if (is_global_type(cur->first))
continue;
if (cur->first == "std_logic_vector")
continue;
if (cur->first == "signed")
continue;
if (cur->first == "unsigned")
continue;
fd << "type " << cur->first << " is ";
cur->second->write_type_to_stream(fd);
@ -90,8 +84,6 @@ void Package::write_to_stream(ostream&fd) const
// Do not include global types in types dump
if (is_global_type(cur->first))
continue;
if (cur->first == "std_logic_vector")
continue;
fd << "type " << cur->first << " is ";
cur->second->write_type_to_stream(fd);