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This commit is contained in:
Nick Gasson 2008-07-21 15:20:40 +01:00
parent 55747bf79d
commit 2f4f075005
1 changed files with 1 additions and 1 deletions
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tgt-vhdl/vhdl.cc
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@ -31,7 +31,7 @@
#include <map>
/*
* Maps a signal to the entity it is defined within. Also
* Maps a signal to the scope it is defined within. Also
* provides a mechanism for renaming signals -- i.e. when
* an output has the same name as register: valid in Verilog
* but not in VHDL, so two separate signals need to be