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https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Implemented %force/x0 instruction using force filter.
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+9
-4
@@ -2376,7 +2376,7 @@ bool of_FORCE_X0(vthread_t thr, vvp_code_t cp)
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// X0 register.
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long index = thr->words[0].w_int;
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vvp_fun_signal_vec*sig = dynamic_cast<vvp_fun_signal_vec*> (net->fun);
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vvp_fun_signal4*sig = dynamic_cast<vvp_fun_signal4*> (net->fun);
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if (index < 0 && (wid <= (unsigned)-index))
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return true;
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@@ -2392,10 +2392,15 @@ bool of_FORCE_X0(vthread_t thr, vvp_code_t cp)
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if (index+wid > sig->size())
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wid = sig->size() - index;
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vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
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vvp_vector2_t mask(vvp_vector2_t::FILL0, sig->size());
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for (unsigned idx = 0 ; idx < wid ; idx += 1)
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mask.set_bit(index+idx, 1);
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vvp_net_ptr_t ptr (net, 2);
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vvp_send_vec4_pv(ptr, vector, index, wid, sig->size(), 0);
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vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
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vvp_vector4_t value(sig->size(), BIT4_Z);
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value.set_vec(index, vector);
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sig->force_vec4(value, mask);
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return true;
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}
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