luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Implemented %force/x0 instruction using force filter.

This commit is contained in:
Stephen Williams 2009-06-08 17:58:59 -07:00
parent 307121d1af
commit 90941648bf
1 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
vvp/vthread.cc
View File

@ -2376,7 +2376,7 @@ bool of_FORCE_X0(vthread_t thr, vvp_code_t cp)
// X0 register.
long index = thr->words[0].w_int;
vvp_fun_signal_vec*sig = dynamic_cast<vvp_fun_signal_vec*> (net->fun);
vvp_fun_signal4*sig = dynamic_cast<vvp_fun_signal4*> (net->fun);
if (index < 0 && (wid <= (unsigned)-index))
return true;
@ -2392,10 +2392,15 @@ bool of_FORCE_X0(vthread_t thr, vvp_code_t cp)
if (index+wid > sig->size())
wid = sig->size() - index;
vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
vvp_vector2_t mask(vvp_vector2_t::FILL0, sig->size());
for (unsigned idx = 0 ; idx < wid ; idx += 1)
mask.set_bit(index+idx, 1);
vvp_net_ptr_t ptr (net, 2);
vvp_send_vec4_pv(ptr, vector, index, wid, sig->size(), 0);
vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
vvp_vector4_t value(sig->size(), BIT4_Z);
value.set_vec(index, vector);
sig->force_vec4(value, mask);
return true;
}