luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update some warning messages.

This commit is contained in:
Cary R 2010-12-14 13:54:34 -08:00 committed by Stephen Williams
parent 43c204ba87
commit 8e2830fe3b
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tgt-vvp/draw_switch.c
View File

@ -106,8 +106,8 @@ void draw_switch_in_scope(ivl_switch_t sw)
break;
default:
fprintf(stderr, "%s:%u: sorry: resistive switch modeling is not "
"currently supported.\n",
fprintf(stderr, "%s:%u: tgt-vvp sorry: resistive switch modeling "
"is not currently supported.\n",
ivl_switch_file(sw), ivl_switch_lineno(sw));
vvp_errors += 1;
return;

2
tgt-vvp/vvp_process.c
View File

@ -1250,7 +1250,7 @@ static void force_link_rval(ivl_statement_t net, ivl_expr_t rval)
}
if (ivl_signal_width(lsig) > ivl_signal_width(rsig) ||
(part_off_ex && get_number_immediate(part_off_ex) != 0)) {
fprintf(stderr, "%s:%u: vvp-tgt sorry: cannot %s signal to "
fprintf(stderr, "%s:%u: tgt-vvp sorry: cannot %s signal to "
"a bit/part select.\n", ivl_expr_file(rval),
ivl_expr_lineno(rval), command_name);
exit(1);