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3943 Commits

Author SHA1 Message Date
Matt Guthaus 0ce2dd2791 Add supply_grid file 2018-08-29 15:34:45 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 04b7c419f1 Rename _new cell back to original for LVS comparison script 2018-08-29 15:34:45 -07:00
Matt Guthaus 5386b7a0f4 Initial refactor of signal and supply router classes. 2018-08-29 15:34:45 -07:00
Matt Guthaus 19d14e39ce Remove extraneous files 2018-08-29 15:34:45 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus 41fba9d27c Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
Michael Timothy Grimes 807a4d7767 Fixed drcs error in magic. Pbitcell should now pass unit tests in calibre and magic. 2018-08-29 15:30:50 -07:00
Hunter Nichols 775fe7b57c Fixed measure statement stating times. This commit crashes if there are no readwrite ports. 2018-08-29 15:13:31 -07:00
Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear 2018-08-29 08:52:45 -07:00
Hunter Nichols 8a0411279e Merge branch 'dev' into multiport_characterization 2018-08-29 01:27:37 -07:00
Hunter Nichols 8fad81ff1e Changed delay measures to add additional measure based on # of ports. Measure times are not correct yet. 2018-08-29 00:43:27 -07:00
Hunter Nichols ffe59bdf51 Edited delay measures to handle multiple readwrite ports. This commit is not well tested. 2018-08-29 00:01:22 -07:00
Matt Guthaus e804f36bec Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
Hunter Nichols fa8434e5f0 Added debug checks for unsupported port options. 2018-08-28 13:01:35 -07:00
Hunter Nichols bd763fa1e3 Fixed naming issue between sram instance and PWL in stimulus 2018-08-28 12:09:02 -07:00
Matt Guthaus 309bfaea2a Update comments in magic to download the correct version of design rules 2018-08-28 11:48:23 -07:00
Matt Guthaus 8752d799b4 Skip pbitcell tests for now 2018-08-28 10:45:50 -07:00
Matt Guthaus 95a8688506 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-28 10:43:45 -07:00
Matt Guthaus 0dbc88dab2 Rename _new cell back to original for LVS comparison script 2018-08-28 10:43:44 -07:00
Matt Guthaus 82833ef8f0 Initial refactor of signal and supply router classes. 2018-08-28 10:43:44 -07:00
Matt Guthaus 8f1e2675fe Remove extraneous files 2018-08-28 10:43:44 -07:00
Matt Guthaus 2ae1e0234d Update router to work with pin_layout structure. 2018-08-28 10:43:44 -07:00
Matt Guthaus ea52af3747 Add sketch for power grid routing code 2018-08-28 10:43:44 -07:00
Matt Guthaus ac8a16ebdf Fix permissions for unit tests to be run standalone. 2018-08-28 10:31:58 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Hunter Nichols 0bb4b48439 Merge branch 'dev' into multiport_characterization 2018-08-28 00:37:26 -07:00
Hunter Nichols 75da5a994b Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports. 2018-08-28 00:30:15 -07:00
Hunter Nichols ba5988ec7f Added write port structure to create_test_cycles. This commit contains test code. 2018-08-27 20:35:29 -07:00
Hunter Nichols d82d3df4a7 Added read port cycle data generation. This commit contains test code in create_test_cycles 2018-08-27 18:17:02 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Hunter Nichols a0e06809f9 Comments now display port in stim file. 2018-08-27 16:23:23 -07:00
Hunter Nichols 350823d434 Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization 2018-08-27 15:56:42 -07:00
Matt Guthaus 9f051df18d Added netlist only configuration option. 2018-08-27 14:33:02 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Matt Guthaus 0daad338e4 All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
Matt Guthaus 87f539f3a8 Separate netlist/layout for flop and precharge array. 2018-08-27 10:54:21 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Michael Timothy Grimes 8c73a26daa Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
Hunter Nichols 6dc72f5b1e Added additional control signal to stim file based on # of ports. 2018-08-23 17:46:24 -07:00
Hunter Nichols efcb435fde Changed # of address signals to reflect # of ports in delay 2018-08-23 14:49:56 -07:00
Hunter Nichols 9151858449 Characterizer now recognizesmultiple ports and additional DIN/DOUT signals are added to stim file. 2018-08-22 23:45:43 -07:00
Hunter Nichols 21e85297d3 Merge branch 'dev' into multiport_characterization 2018-08-22 14:50:29 -07:00
Hunter Nichols 8abf45a5d3 Some test code added. To be removed later. 2018-08-22 14:19:09 -07:00
Michael Timothy Grimes b8ae21a52b made multi-port changes to sram. This commit will allow all levels of openram to pass unit tests 2018-08-20 22:11:24 -07:00
Michael Timothy Grimes f0cca8293c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-19 00:01:52 -07:00
Michael Timothy Grimes 8e3dc332f3 changed control signal names in bank select to accommodate multi-port changes in bank 2018-08-19 00:00:42 -07:00
Michael Timothy Grimes 19ca0d6c2a Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port 2018-08-18 16:51:21 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Matt Guthaus e3f2ee8a7e Fix VCG error in channel route. 
Note, the channel routing algorithm still does not handle
horizontal conflicts or cyclic vertical conflicts!
 2018-08-15 14:19:04 -07:00
Matt Guthaus 6e332e581a Updated to include local magic rules 2018-08-15 09:46:23 -07:00
Michael Timothy Grimes e147f807a5 adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet 2018-08-15 04:32:56 -07:00
Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist. 2018-08-15 04:00:48 -07:00
Michael Timothy Grimes e592d95146 Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist. 2018-08-15 03:36:40 -07:00
Michael Timothy Grimes a5af4a2b9c resolved variable name error in 00_code_format test 2018-08-15 03:33:33 -07:00
Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called 2018-08-15 02:19:36 -07:00
Michael Timothy Grimes 040340b49f editted naming convention on precharge to accommodate multiport 2018-08-15 02:14:45 -07:00
Michael Timothy Grimes 8d97862f6e altered precharge array and precharge unit tests to accommodate multiport 2018-08-15 00:55:23 -07:00
Matt Guthaus 36bfd2932a Update delay results with new clock routing 2018-08-14 10:51:02 -07:00
Matt Guthaus 8900edbe12 Finalize single bank clock routing. 2018-08-14 10:36:35 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus 5ff49d322d bank_sel_bar only used for clk now 2018-08-13 15:14:52 -07:00
Matt Guthaus f7f318d72e Remove tri_en signals from bank control logic. 2018-08-13 14:47:03 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 9ffba4b052 Add +x permissions on precharge and pbitcell tests 2018-08-13 09:57:10 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus abacf6a2d0 Add carriage return check for python files 2018-08-07 09:40:45 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus c0d5f781cf Not sure how VCG channel constraint got removed. Fixed this bug before... 2018-07-27 15:15:40 -07:00
Matt Guthaus a7a3099702 Fix comments in stimulus file to show list and not zip type 2018-07-27 15:00:00 -07:00
Matt Guthaus d739c17b8d Fix delay numbers in hspice delay unit test. 2018-07-27 14:43:52 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting 2018-07-27 14:07:55 -07:00
Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure. 2018-07-27 14:06:59 -07:00
Matt Guthaus 8f72621f4a Converted delay measurement to use add_read/add_write functions. 
Rewrote the logic to add one cycle at a time for easier
manipulation. This can be extended more easily into the
functional simulations.
 2018-07-27 11:36:17 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus 01cbc71a2a Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
Matt Guthaus b541efe959 Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv. 2018-07-27 07:23:18 -07:00
Matt Guthaus 0e0516c4a6 Fix delay test unit test results. 2018-07-26 16:45:09 -07:00
Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly 
copy into unit test. Factor function into testutils.py for comparison.
 2018-07-26 16:05:24 -07:00
Matt Guthaus 5088487cf7 Update delay tests to output useful information for debug. 2018-07-26 15:45:17 -07:00
Matt Guthaus a00e160274 Convert bitline index to integer in trim_spice 2018-07-26 14:29:44 -07:00
Matt Guthaus f098b995f0 Fix pinvbuf test to use new interface with only driver size. 2018-07-26 14:20:00 -07:00
Matt Guthaus c8808c268a Close output log in test 30 to avoid warning 2018-07-26 14:01:40 -07:00
Matt Guthaus bc67ad5ead Fixed timing to be measured from positive clock edge since 
reading a 1 will be the precharge time.
Started modifying the lib file for DIN and DOUT ports, but did not
check the syntax yet.
 2018-07-26 13:58:50 -07:00
Matt Guthaus e827c1b8c7 Make pinvbuf have unique names for GDS compliance. 
Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
 2018-07-26 11:40:40 -07:00
Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the 
clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.
 2018-07-26 11:28:48 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus dd7069dd98 Remove print statement 2018-07-25 15:51:48 -07:00
Matt Guthaus b7525a14c2 Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch. 2018-07-25 15:50:49 -07:00
Matt Guthaus d6df215718 Always use m2_pitch as default for channel for via spacing rules 2018-07-25 15:47:11 -07:00
Matt Guthaus 6d71c3f790 Fix bug to remove pin from conflicts in addition to graph keys 2018-07-25 15:36:16 -07:00
Matt Guthaus a4bfbe3545 Move dff_array pins to center of rail 2018-07-25 15:08:04 -07:00
Matt Guthaus 44f0e4a1de Fix new offset coordinate syntax error 2018-07-25 13:47:36 -07:00
Matt Guthaus 64b3cfee26 Only print LVS/DRC stats when it is enabled 2018-07-25 13:44:34 -07:00
Matt Guthaus 7c254d540d Change channel route api to use pin maps instead of an insteads for cases where there are multiple instances that have the pins (e.g. decoders) 2018-07-25 11:37:06 -07:00
Matt Guthaus f7a2766c29 First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels. 2018-07-25 11:13:30 -07:00
Matt Guthaus 48d3b25b74 Rotate the output pins of the control logic. Need to fix this permanently. 2018-07-24 14:26:01 -07:00
Matt Guthaus 16a084fde1 Add vdd/gnd at right end of rails. Rename some signals for clarity. 2018-07-24 14:15:11 -07:00
Matt Guthaus aa2ea26db3 Convert control module to use hierarchy bus API 2018-07-24 10:35:07 -07:00
Matt Guthaus b50f57ea3a Remove control logic supply rails and replace with M3 supply pins 2018-07-24 10:12:54 -07:00
Matt Guthaus 45a53ed089 Rotate via in center for freepdk 2018-07-19 14:01:48 -07:00
Matt Guthaus 4c3bd0e42b Move WL gnd contacts outside the cell for simplicity 2018-07-19 13:38:45 -07:00
Matt Guthaus beee8229d1 Revert change. Add gnd pin to right on bitline load. 2018-07-19 13:26:12 -07:00
Matt Guthaus ea53066966 Align RBL inverter with first load inverter in delay chain to aid supply connections 2018-07-19 11:02:13 -07:00
Matt Guthaus 311ab97bfc Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections. 2018-07-19 10:51:20 -07:00
Matt Guthaus 128dfd5830 Add internal vdd/gnd connections for delay chain 2018-07-19 10:37:47 -07:00
Matt Guthaus 51958814a0 Fixing power via problems in freepdk45 2018-07-19 10:23:08 -07:00
Matt Guthaus 9983408fa3 Add verilog_write to sram wrapper for verilog unit test 2018-07-19 10:05:30 -07:00
Matt Guthaus 3f57853969 Use lower case names except for leaf cells and top level 2018-07-18 15:10:57 -07:00
Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Matt Guthaus a9c0ec5549 Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
Matt Guthaus a878ce5500 Standardize DRC and LVS message levels 2018-07-18 14:28:43 -07:00
Matt Guthaus 58896a6f8e Fix control signal names on control_logic input 2018-07-18 13:41:44 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus 6133d54684 Fix spacing between adjacent decoders 2018-07-17 15:01:16 -07:00
Matt Guthaus ffc866ef78 Single bank working except for channel routing error in 4-way case. 2018-07-17 14:40:04 -07:00
Matt Guthaus 7a69fc1bca Add col addr routing and data routing 2018-07-17 14:24:44 -07:00
Matt Guthaus 0665d51249 Must connect clock at top level for now 2018-07-17 14:24:07 -07:00
Matt Guthaus e82f97cce1 Add create_bus and connect_bus api 2018-07-17 14:23:29 -07:00
Matt Guthaus 0175c88a16 Convert predecodes to use create_bus api 2018-07-17 14:23:06 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus 77e786ae5e Fix bug in recomputing boundary with a new offset 2018-07-16 13:46:12 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 93e830e800 Add new supplies to replica bitline 2018-07-16 10:49:43 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Matt Guthaus 0c23efe49b Reference local sram instance in sram.py. 2018-07-13 09:30:14 -07:00
Michael Timothy Grimes 2388ddbfb0 deleting code added in error to pbitcell_array_test during previous commit 2018-07-12 23:55:54 -07:00
Michael Timothy Grimes ba43b986ae merging changes with pbitcell_array test 2018-07-12 23:51:44 -07:00
Michael Timothy Grimes a64ca423c6 changing pbitcell_array test to include an important permutation of the design 2018-07-12 23:45:47 -07:00
Michael Timothy Grimes 7b315a3b69 updating inverter to write transistor spacings 2018-07-12 20:52:05 -07:00
Matt Guthaus a4c29ea527 Improve openram output. Fix save output function name. 2018-07-12 10:35:38 -07:00
Matt Guthaus e6b1fcb44c Refactor banks to use inheritance with a top-level SRAM wrapper class. 2018-07-12 10:30:45 -07:00
Matt Guthaus c71ea51e2e Merge branch 'multiport_cleanup' of github.com:VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:41 -07:00
Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:06 -07:00
Matt Guthaus a2d8d16c7a Split DATA into DIN and DOUT in characterizer 2018-07-11 14:19:09 -07:00
Matt Guthaus 33bb98894f Disable LEF test until supplies fixed. 2018-07-11 14:18:53 -07:00
Matt Guthaus 8be88d14a7 Disable banner output during gitlab runner 2018-07-11 14:18:36 -07:00
Matt Guthaus 7d8352a04d Fix order of checkpointing so that it is done after characterizer and verify have found their executables. 2018-07-11 12:12:03 -07:00
Matt Guthaus 8a530da2cc Remove extra conversion to list 2018-07-11 12:07:37 -07:00
Matt Guthaus 265b5d977a Fix option reload problems and checkpointing so that it works properly. 2018-07-11 12:00:15 -07:00
Matt Guthaus 58646ab8e6 Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
Matt Guthaus f894ef47af Fix missing list conversion to run drc library tests. 2018-07-11 11:58:22 -07:00
Matt Guthaus b3732f4fcf Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
Matt Guthaus f82591dd6f Remove outdated README 2018-07-11 09:12:20 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus d95a1925d4 Refactor banked SRAM into multiple files and dynamically load in SRAM 2018-07-10 14:17:09 -07:00
Matt Guthaus 19c53cd50c Do not fail assertion in exception code. 2018-07-10 14:16:18 -07:00
Matt Guthaus 707f303eb7 Fix syntax error in sram.py 2018-07-10 10:34:54 -07:00
Matt Guthaus f5855ee68a Fix analytical power of contact with new hierarchy_design level introduced. 2018-07-10 10:17:23 -07:00
Matt Guthaus 25cf57ede5 Push create bus functions down into layout class. 2018-07-10 10:06:59 -07:00
Matt Guthaus 98f1914e9f Fix width of decoder with new input bus. Bank tests work again. 2018-07-10 09:31:41 -07:00
Matt Guthaus 019512bc25 Fix python3 module reference in functional test 2018-07-09 16:07:53 -07:00
Matt Guthaus f234e43241 Reset new hierarchy_design instead of design for duplicate GDS name checker 2018-07-09 16:07:30 -07:00
Matt Guthaus bbc98097ac Add getpass include to unit test 30 2018-07-09 15:53:37 -07:00
Matt Guthaus 7bf271fd63 Skip pex and functional tests which are not working. 2018-07-09 15:52:07 -07:00
Matt Guthaus 9d5e5086a1 Add new extra design class with additional hierarchy for shared design rules 2018-07-09 15:43:26 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus 2e5d60ae87 Fix input height error for input rail pins 2018-07-09 14:45:27 -07:00
Matt Guthaus e60d157310 Add input pin rails to hierarchical decoder for easier connections at SRAM level. 2018-07-09 13:16:38 -07:00
Matt Guthaus 5cf62e82cf Merge branch 'dev' into multiport_cleanup 2018-07-09 09:58:13 -07:00
Matt Guthaus af84742c19 Simplify m2 pitch calculation 2018-07-09 09:57:57 -07:00
Matt Guthaus a9a95ebf7c Fix pex test permissions 2018-07-09 09:11:14 -07:00
Matt Guthaus b3dc6560f5 Remove regress.sh script 2018-07-09 09:10:12 -07:00
Matt Guthaus 5d32a426c4 Change test sram path so jobs can be simultaneously run. 2018-07-06 07:34:38 -07:00
Matt Guthaus 733be110a2 Add negation to return code so tests fail or pass properly. 2018-07-06 07:27:26 -07:00
Matt Guthaus 7c6974dd08 Fix options so it is in /tmp in RAM drive 2018-07-05 16:33:26 -07:00
Matt Guthaus 3260468477 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 16:27:49 -07:00
Matt Guthaus 077f3f20ec Add return code for regression test 2018-07-05 16:27:47 -07:00
Matt Guthaus cc815f4c33 Fix sense amp spacing after modifying index to be increment by one. 2018-06-29 15:30:17 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Matt Guthaus 6ac24dbf0c Fix module name for python3 2018-06-29 15:12:15 -07:00
Matt Guthaus 3de81c8a67 Close files in trim spice and delay. 2018-06-29 15:11:41 -07:00
Matt Guthaus 8d61ccbc6f Convert byte string to string. 2018-06-29 15:11:14 -07:00
Matt Guthaus 6cd1779f7b Rename pex test so that it ends with _test and will be run by regress.py. 2018-06-29 12:47:22 -07:00
Matt Guthaus 32099646cf Add back fix to revert bitcell from pbitcell. 2018-06-29 12:45:26 -07:00
Matt Guthaus a9849eff3a Merge in mtgrime's fix. 2018-06-29 12:44:26 -07:00
Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-06-29 12:07:03 -07:00
Michael Timothy Grimes 721f935d66 changing pbitcell tests to revert OPTS.bitcell to bitcell after tests 2018-06-29 12:00:36 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus fa17d5e7f3 Change permissions of tests to be executable so you don't have to type python each time. 2018-06-29 11:36:30 -07:00
Matt Guthaus 69921b0844 Add enclosing well to column mux. Move well contact to cell boundary. 2018-06-29 11:35:29 -07:00
Matt Guthaus 3becf92e7c Combine pbitcell tests into one unit test 2018-06-29 10:00:23 -07:00
Matt Guthaus df2dce2439 Fix module import names for python3. Rename parse function to something meaningful. 2018-06-29 09:45:07 -07:00
Matt Guthaus 8cee26bc8c Allow python 3.5. Make easier to revise required version. 2018-06-29 09:23:43 -07:00
Matt Guthaus 2833b706c7 Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass. 2018-06-29 09:23:23 -07:00
Michael Timothy Grimes d7a024b8fc adding another important port combination to unit tests 2018-06-03 19:36:48 -07:00
Michael Timothy Grimes fea304eac1 corrected gate to contact spacing 2018-05-31 18:31:34 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 9e739d67d4 python 3 changes d.iterkeys() -> iter(d.keys()) 2018-05-29 11:54:10 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes 17769f27c6 small changes to pbitcell 2018-05-22 14:51:42 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Michael Timothy Grimes 5e4d4bf6cd resolved conflicts with bitcell_array after PrivateRAM merge 2018-05-22 14:12:14 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 58628d7867 Merge branch 'multiport_cleanup' into dev 2018-05-11 09:23:43 -07:00
Matt Guthaus 0e35937da5 Commit local changes. Forgot what the status is. 2018-05-11 09:15:29 -07:00
Matt Guthaus b14bef3bcf Initial merge of incomplete multi-port clean with new supply routing. 2018-05-11 08:18:04 -07:00
Michael Timothy Grimes 3971835f24 changed pbitcell_array tests in regards to addition of read/write ports in pbitcell 2018-05-10 09:40:43 -07:00
Michael Timothy Grimes 7af95e4723 adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports. 2018-05-10 09:38:02 -07:00
Matt Guthaus 7b5791b0e9 Change tolerance of tests to a big value. Update tests. 2018-05-09 08:29:23 -07:00
Michael Timothy Grimes 683f5fb9fc adding variable for w_ports to be used in multiport design 2018-04-26 14:03:48 -07:00
Michael Timothy Grimes 7d3f7eefac syntax corrections to pbitcell and modifying transistor sizes 2018-04-26 14:03:03 -07:00
Matt Guthaus 875eb94a34 Move bank select below row decoder, col mux, or col decoder. 2018-04-23 12:17:16 -07:00
Matt Guthaus e04f53dc27 Rotate via 2018-04-23 09:18:34 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus cd502895c4 Undoing last change. 2018-04-23 08:48:50 -07:00
Matt Guthaus 8ce3809cad Divide index 2018-04-20 17:09:15 -07:00
Matt Guthaus ed76a784d2 Remove power rails and ring. 2018-04-20 15:51:19 -07:00
Matt Guthaus 19a957a57c Fix unattached label on sense amp out by changing layer. 2018-04-20 15:48:38 -07:00
Matt Guthaus d734c05b71 Fix missing vdd pins and fix routing between sense amp, bitcell array and column mux. 2018-04-20 15:47:21 -07:00
Matt Guthaus df9bdccd45 Change lvs check to look only at the last/top module. 2018-04-20 15:46:12 -07:00
Matt Guthaus 929122b6dc Change default to scmos. Refactor add column mux. 2018-04-20 12:52:41 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus 63a8f7c653 Remove m2 from write driver 2018-04-16 16:15:35 -07:00
Matt Guthaus bb1ec63c4f Removed msf data flop from bank 2018-04-16 16:03:46 -07:00
Matt Guthaus 1ba87c88f5 Remove supply rails in decoder 2018-04-16 15:59:52 -07:00
Matt Guthaus 13adfc3724 Add bank ground routing 2018-04-16 10:15:36 -07:00
Matt Guthaus 3fe4578feb Change stages of delay to odd 2018-04-16 10:15:15 -07:00
Matt Guthaus 70c92c27ef Supply to M3 for bank select logic 2018-04-11 16:55:09 -07:00
Matt Guthaus 010a187545 Remove dead logic 2018-04-11 16:54:55 -07:00
Matt Guthaus e038561b4a Move supply to M3 in wordline driver 2018-04-11 16:23:45 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 1e36e8e20c Fix ms_flop array for M3 supplies 2018-04-11 14:25:04 -07:00
Matt Guthaus 873be38e15 Add M3 pins on dff_buf array 2018-04-11 12:09:15 -07:00
Matt Guthaus 4971dde316 Rename pin variable 2018-04-11 12:08:57 -07:00
Matt Guthaus fa59b3d33d Copy predecoder supply pins 2018-04-11 11:56:41 -07:00
Matt Guthaus 1afb0a1d86 Add M3 supply vias to decoder. 2018-04-11 11:47:37 -07:00
Matt Guthaus 3ba90c035f Don't bring M2 rails over supply to allow supply connections. 2018-04-11 11:47:22 -07:00
Matt Guthaus f3baf48c22 Rotate vias in hierarchical predecodes 2018-04-11 11:12:32 -07:00
Matt Guthaus 424eb17921 Add M3 pins to hierarchical predecodes 2018-04-11 11:10:34 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus 91e342e4c9 Move precharge vdd pin to left edge. 2018-04-04 15:03:29 -07:00
Matt Guthaus a772217172 Route precharge_array vdd in M3 2018-04-04 13:49:55 -07:00
Matt Guthaus f9916f9f43 Route precharge vdd to M3 2018-04-04 13:34:56 -07:00
Matt Guthaus 4c4cfb2a3c Add local dir for output. Will remove later. 2018-04-04 09:55:32 -07:00
Michael Timothy Grimes 7f46a0dead merging changes in bitcell.py 2018-04-03 09:46:12 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 5bf915a232 Detect via size for power ring. 2018-03-23 08:13:28 -07:00
Matt Guthaus ed2fa10caa Use LSB for column mux. 
Detect via size for power ring.
 2018-03-23 08:13:20 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Michael Timothy Grimes 0cc077598e Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell. 2018-03-15 12:02:38 -07:00
Michael Timothy Grimes 65735c08e2 fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters 2018-03-08 16:39:26 -08:00
Michael Timothy Grimes 0ea5d0b6a7 making changes to bitcell_array to account for the addition nets from the multiported bitcells 2018-03-06 17:03:21 -08:00
Michael Timothy Grimes 820a8440c9 adding unit test for bitcell array using pbitcell 2018-03-06 16:36:11 -08:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 1eda3aa131 Add back offset all coordinates in sram.py. 2018-03-05 14:22:24 -08:00
Matt Guthaus ba82222475 Add bank_select module option 2018-03-05 14:06:12 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 0c203c1c7e RBL width is max of delay chain or bitcell load. 2018-03-05 10:23:13 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 0f721a3d40 Add vdd and gnd rails around bank structure. 2018-03-04 17:53:22 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
Matt Guthaus 242a1a68e0 Fix duplicate instance gds output bug that only showed up in Magic extraction. Every time we saved a GDS, additional instances were put in the GDS file. Most extraction tools ignored this, but Magic actually extracted duplicates. 2018-03-02 18:05:46 -08:00
Matt Guthaus 2b130de198 Rewrite run_lvs.sh script to utilize setup.tcl file. 2018-03-02 18:03:55 -08:00
Michael Timothy Grimes fc294cb282 Fixed cell height and width 2018-03-02 10:53:29 -08:00
Michael Timothy Grimes d33dec4e9e Separated add_globals function into add_ptx and add_globals 2018-03-02 10:49:26 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Michael Timothy Grimes d6ef91786b updating pbitcell with latest layout optimizations 2018-02-28 17:56:13 -08:00
Hunter Nichols 93ad99b9e1 Changed variable names in analytical power function to be more clear. 2018-02-28 12:32:54 -08:00
Hunter Nichols 6a3f0843ff Fixed accidental changes made to analytical delay. 2018-02-28 12:18:41 -08:00
Michael Timothy Grimes 1ba626fce1 removed pbitcell for compiler folder 2018-02-28 11:28:04 -08:00
Michael Timothy Grimes d41abb3074 moved pbitcell to new folder for parametrically sized cells 2018-02-28 11:25:22 -08:00
Michael Timothy Grimes 4d3f01ff2f The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS 
There are 2 benchtests for the bitcell:
1) one with 2 write ports and 2 read ports
2) one with 2 write ports and 0 read ports
The second test is meant to show how the bitcell functions when read/write ports are
used instead of separate ports for read and write
The bitcell currently passes both tests in both technologies
Certain sizing optimizations still need to be done on the bitcell
 2018-02-28 11:14:53 -08:00
Michael Timothy Grimes bf7d846e5f Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-28 04:29:38 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 35137d1c67 Add extra comments in stimulus output. 2018-02-26 14:39:06 -08:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus 7a14cf16e0 Change priority of debug info for DRC/LVS. 2018-02-25 11:14:31 -08:00
mguthaus 322f354878 Convert period to float to avoid type mismatch. 2018-02-25 11:13:43 -08:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
Matt Guthaus d88ff01792 Change default operating conditions to OC 2018-02-23 13:38:55 -08:00
Matt Guthaus 29aa6002e6 Make period into p instead of remove it. Changes file names... 2018-02-23 12:50:02 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus 107752b1fb Fix num words in example. 2018-02-23 12:17:43 -08:00
Matt Guthaus e3e7a31c6b Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Matt Guthaus 23f06bfa9a Reduce number of parameters in function calls for delay.py. 2018-02-22 11:14:58 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 71831e7737 Get delays only for successful run. 2018-02-21 14:05:39 -08:00
Matt Guthaus 9600dae7df Remove print statements. 2018-02-21 13:45:14 -08:00
Matt Guthaus 7d2f4386e2 Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit. 2018-02-21 13:38:43 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Michael Timothy Grimes 4ea2a70a1b removing unnecessary unit test for pbitcell 2018-02-19 10:58:08 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
mguthaus 28fe49d069 Change RBL to allow stages and FO for configuration 2018-02-16 11:51:01 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
mguthaus cb449a1cd2 Ignore non-rectangular pins. 2018-02-16 10:24:57 -08:00
Matt Guthaus 2e3e95efda Change ratio of delay line and RBL size. Need to tune it better automatically. 2018-02-14 16:50:08 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus f457091bba Fix typo in precharge. 2018-02-12 15:34:01 -08:00
Matt Guthaus e32b0b8f7a Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
mguthaus e210d3d49a Make some common lib memory sizes. Update Makefile to auto build and char them all. 2018-02-12 12:00:59 -08:00
mguthaus 636099c5e1 Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
mguthaus 1795dc5677 Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00
Michael Timothy Grimes 72fc92ad95 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-11 16:47:53 -08:00
mguthaus f690532563 Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
Matt Guthaus 4dd075c7b7 Add V and C to names of lib files. 2018-02-11 16:34:32 -08:00
Matt Guthaus ce164fb7a8 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-10 10:03:26 -08:00
Matt Guthaus b75eef3684 Fix syntax error. 2018-02-10 08:02:59 -08:00
Matt Guthaus 4d35972553 Get default corner options from tech file 2018-02-09 15:49:55 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus d19867e64c Move utils to base. 2018-02-09 10:42:23 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00
Matt Guthaus 7c83ef3f04 Fix missing subdir name. Comment about organization. 2018-02-09 10:27:43 -08:00
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
Matt Guthaus 489faaba99 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-09 10:20:56 -08:00
Matt Guthaus 13fd87d99e Accidentally committed to master. Merge branch 'master' into dev 2018-02-09 10:19:22 -08:00
Matt Guthaus d62da44329 Fix bug where path does not obey specified width. 2018-02-09 10:03:09 -08:00
mguthaus 5aa92a6549 Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
mguthaus 8719a19377 Move parameter setting to config reading rather than status function. 2018-02-09 09:26:13 -08:00
Matt Guthaus 3c86f94549 Change argument name for lib in tests as well. 2018-02-08 15:28:49 -08:00
Matt Guthaus d684189241 Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
Michael Timothy Grimes ce83b67350 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-08 14:27:53 -08:00
Michael Timothy Grimes b90f5c9a59 pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd 
current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports
 2018-02-08 14:21:15 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
Matt Guthaus 54c21f6282 Added method=gear back to ngspice simulation to fix convergence bug. 2018-02-07 21:07:11 -08:00
mguthaus e8f658d356 Add updated non-pruned unit test results. 2018-02-07 19:35:21 -08:00
mguthaus 63ce754c72 Update unit test results 2018-02-07 18:48:22 -08:00
Matt Guthaus 1b4be741df Fix broken print statements 2018-02-07 17:39:42 -08:00
Matt Guthaus 9cc46453a2 Fix PWL bug to output last value. Fix bug in setup/hold use of improved PWL function. 2018-02-07 15:43:09 -08:00
Matt Guthaus 2413304f4e Update replica bitline test for new parameters. Add small test and a larger test. 2018-02-07 15:15:19 -08:00
Matt Guthaus 1a491f3cd0 Make temp directory unique for test 30. Update LEF files after delay chain size change. 2018-02-07 15:05:21 -08:00
Matt Guthaus e93517529c Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive. 2018-02-07 14:54:59 -08:00
Matt Guthaus 8e91552701 Remvoe newline. 2018-02-07 14:33:29 -08:00
Matt Guthaus 5dacafc698 Disable gear integration in ngspice. Not sure it is necessary anymore and it is quite slow. 2018-02-07 14:20:15 -08:00
Matt Guthaus a2bf66b063 Add metal1 gnd line to prevent DRC errors when sizing delay chain. 2018-02-07 14:15:13 -08:00
Matt Guthaus 3e4ef36efe Clean up Python comments and improve comments in stimulus file. 2018-02-07 14:04:18 -08:00
Matt Guthaus 3820861ce8 Increase control delay line from 4 inverters to 3 FO4 delays. Need to dynamically adjust this. 2018-02-07 13:10:45 -08:00
Matt Guthaus 5c4999d4cc Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic. 2018-02-07 12:58:47 -08:00
Matt Guthaus 8e91faaccb Remove version from OpenRAM. We will go bit git hashes. 2018-02-06 10:56:26 -08:00
mguthaus 3af1bbba26 Updated delay tests with new delays including ps, pd, as, ad. 2018-02-06 07:58:25 -08:00
mguthaus c3592b3d46 Added new timing tests with ps,pd,as,ad caps included. 2018-02-06 05:26:27 -08:00
Matt Guthaus 33b04bbca5 Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements. 2018-02-05 16:02:57 -08:00
Matt Guthaus 941094ce31 Return slews to 10-90 and 90-10 so I don't have to re-hardcode the results in unit tests. 2018-02-05 15:21:53 -08:00
Matt Guthaus 4505c0f74e Improve error to setup model dir path. Use it to override FreePDK45 too. 2018-02-05 15:12:12 -08:00
Matt Guthaus 85f4438280 Exit with error if model files are not found. 2018-02-05 15:09:21 -08:00
mguthaus e01d5b7c61 Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
Matt Guthaus e2e5f45cec Correct vague comments about char cycles. End simulation after last period even though a transition would mean a failed simulation. 2018-02-05 14:07:12 -08:00
Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge. 2018-02-05 11:36:46 -08:00
Matt Guthaus 92095e52f7 Update new LEF files for unit tests. 2018-02-05 10:27:56 -08:00
Matt Guthaus f21ff38cae Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working. 2018-02-05 10:22:38 -08:00
Matt Guthaus 84b42b0170 Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
Matt Guthaus 7127895270 Update LEF files for unit tests 2018-02-02 15:51:29 -08:00
Matt Guthaus d6d96907ef Route to the right in the bank decode for DRC. 2018-02-02 15:50:45 -08:00
Matt Guthaus 1415d139a3 Specify file format for sp spice extension. 2018-02-02 15:33:35 -08:00
Matt Guthaus 3873f72a58 Ensure wells are spaced in the bank select and column decoder 2018-02-02 15:26:15 -08:00
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Matt Guthaus 74064fc854 Replace LEF files with new changes. 2018-02-02 12:31:34 -08:00
Matt Guthaus e8d001a3f9 Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-02 12:31:33 -08:00
Matt Guthaus e4295ea61b Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-02-02 12:31:33 -08:00
Matt Guthaus 3e2d4d631d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-02-02 12:31:33 -08:00
Matt Guthaus 7c9c16e29c Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-02-02 12:31:33 -08:00
Matt Guthaus cc987daeb9 Add well around column muxes. 2018-02-02 12:31:33 -08:00
mguthaus 2ad52205c5 Clean up messages. 2018-02-02 12:31:33 -08:00
mguthaus d0c9382d97 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-02-02 12:31:33 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 5527e73db0 Add descriptive exceptions along with cleanup in unit test checking. 2018-02-02 12:31:33 -08:00
Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-02-02 12:31:33 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Michael Timothy Grimes fb2572bd71 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-01-28 21:44:22 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus fcc533ec11 Initial LVS using netgen. pinv nad pnand2 pass. No property checks in LVS yet. 2018-01-17 16:48:35 -08:00
Matt Guthaus ba489f0291 Only check if using magic with freepdk when LVSDRC is enabled. 2018-01-17 07:38:29 -08:00
Matt Guthaus 7c50708158 Check that we are not using Magic for FreePDK45. 2018-01-12 14:50:35 -08:00
Matt Guthaus 243097cb33 Remove print statement in magic.py 2018-01-12 14:45:11 -08:00
Matt Guthaus 1b30eb4b64 Initial DRC with Magic is done. 2018-01-12 14:39:42 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus e0a6b59773 Fix LEF test mismatch in regression. 2018-01-12 08:54:31 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Michael Timothy Grimes 64e7ed5b5e Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports 
Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.
 2018-01-09 13:39:42 -08:00
Matt Guthaus f028436156 Add implant/select enclosure rule to ptx. 2018-01-08 12:27:50 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 547746f839 Merge branch 'dev' 2018-01-05 08:34:47 -08:00
Matt Guthaus fd748b4fe4 Move info messages about modes to better locations. 2018-01-05 08:32:23 -08:00
Matt Guthaus 4885616bec Remove metal3 in LEF library cells. 2017-12-19 13:12:39 -08:00
Matt Guthaus 97a2d620fe Fix dev tests. Split pruned test to separate golden result. 2017-12-19 11:42:11 -08:00
Matt Guthaus ee7bf7c5f2 Remove metal3 blanket blockage on library cells. 2017-12-19 09:55:59 -08:00
Matt Guthaus 40465d6518 Merge tolerance change from master. 2017-12-19 09:17:43 -08:00
Matt Guthaus 9059a15ceb Remove tab in lef file. 2017-12-19 09:14:59 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
mguthaus 13902538ff Increase lib file tolerance to 25 percent. 2017-12-19 07:41:08 -08:00
mguthaus f98155fc0b Increase lib file tolerance to 25 percent. 2017-12-19 07:39:43 -08:00
Matt Guthaus 317f2d1293 Merge update master and dev. 2017-12-18 08:13:59 -08:00
Matt Guthaus a4a9205a56 Change thresholds to 50 percent. 2017-12-15 08:02:48 -08:00
Matt Guthaus ed4ca62dbf Update thresholds to 15 percent. Fix ngspice data. 2017-12-15 08:01:19 -08:00
Matt Guthaus 7e091fc622 Increase threshold to 30% for SCMOS 2017-12-14 16:52:49 -08:00
Matt Guthaus e9005add14 Fix tests that were failing. 2017-12-14 15:43:05 -08:00
Matt Guthaus 819e249526 Remove nor_2 reference 2017-12-12 19:25:35 -08:00
Matt Guthaus e3a6c1ac6b Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947. 2017-12-12 15:50:45 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
Matt Guthaus 1085497476 Fail when using Magic/netgen for DRC/LVS. Remove arguments in running precharge test. 2017-12-12 13:06:01 -08:00
Matt Guthaus 8df46abb30 Move nmos gate to the top of the ptx. 2017-12-01 08:31:16 -08:00
Matt Guthaus 45ae8c7315 Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules. 2017-11-30 16:02:32 -08:00
Matt Guthaus 74a22fb515 Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules. 2017-11-30 16:02:17 -08:00
Matt Guthaus 44faa8d58d Fixed SCMOS bugs. 2017-11-30 15:58:16 -08:00
Matt Guthaus c4ce646b81 Fix min height check for scmos 2017-11-30 13:42:55 -08:00
Matt Guthaus c7ff58cef3 Round finger widths to grid. 2017-11-30 12:15:20 -08:00
Matt Guthaus 107cad15a1 Change layout function names to be consistent. 2017-11-30 12:01:04 -08:00
Matt Guthaus 0214cfb48e Fix single finger ptx bugs. 2017-11-30 11:56:40 -08:00
Matt Guthaus 6207f2157c Fix gnd vdd rail overlap bugs. 2017-11-30 09:18:28 -08:00
Matt Guthaus de5c736cb4 Remove temp directory change. 2017-11-29 16:15:22 -08:00
Matt Guthaus 9abe82b203 Pinv implemented, but not DRCed. More new unit tests added for pinv. 2017-11-29 16:11:15 -08:00
Matt Guthaus 13008e1de4 Split pinv unit tests. 2017-11-29 13:43:50 -08:00
Matt Guthaus 1bcef7e3ee Prune ptx code. Change sizes to be relative to min size. 2017-11-29 12:31:00 -08:00
Matt Guthaus d4f8d63442 Fix bug for even number of fingers. Add even finger tests. 2017-11-29 09:44:40 -08:00
Matt Guthaus 7ff82a2aed Improved ptx code but removed internal active/poly positions. 2017-11-28 18:13:32 -08:00
mguthaus 09ca8ba17d Improve output format. Rename option to be more sensible. 2017-11-22 15:57:29 -08:00
Matt Guthaus cf66c83fe4 Fixed address bug to simulate correct wordline 2017-11-21 13:57:59 -08:00
Matt Guthaus aa4768bf87 Add time info for spice simulation calls. 2017-11-21 13:04:18 -08:00
Matt Guthaus 6873342748 Prepend the config file path so it imports your local copy rather than example_config_freepdk, for example. 2017-11-20 11:57:41 -08:00
Matt Guthaus 76ea89e06f Merge branch 'magic_netgen_support' into dev 2017-11-16 13:57:18 -08:00
Matt Guthaus 88740c107f Improve global and code structure using modules. 
Comment and reorganize globals.py
Tests consistently use globals module for OPTions.
Add characterizer as module support.
Modify unit tests to reload new characterizer for ngspice/hspice.
Enable relative and absolute config file arguments so you can run
openram from anywhere on any config file.
 2017-11-16 13:52:58 -08:00
Matt Guthaus 347f1f97fd Merge branch 'master' into magic_netgen_support 2017-11-15 17:05:38 -08:00
mguthaus 2eb9f5c6bc Move verify into a module. Make characterizer a module. Move exe searching to modules. 2017-11-15 17:02:53 -08:00
Matt Guthaus 658f794b12 Add draft of assura DRC/LVS 2017-11-15 12:07:10 -08:00
Matt Guthaus f6410e0371 Merge branch 'master' into dev 2017-11-15 11:46:11 -08:00
Matt Guthaus 75a3884568 Remove tab 2017-11-15 11:45:55 -08:00
Matt Guthaus f123a3ca40 Merge branch 'master' into dev 2017-11-15 07:43:56 -08:00
Matt Guthaus 102db4fecf Fixed prune unit test by relaxing tolerance. 2017-11-15 07:43:43 -08:00
Matt Guthaus 37edd7cac6 Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py. 2017-11-14 16:24:26 -08:00
Matt Guthaus 4285e576f8 Change error to warning for magic/netgen. 2017-11-14 15:49:47 -08:00
Matt Guthaus 40410cc9f5 Clean up code to work when no drc/lvs/pex is found. 2017-11-14 15:31:58 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 70ab672c5c Pad strings in GDS to even number of bytes per bug report. 2017-11-14 14:30:00 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Jun Chen 054e4d3c28 my change 2017-11-11 16:54:04 +09:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 0744cbcc60 Merge branch 'master' into dev 2017-11-09 09:11:26 -08:00
Matt Guthaus 05158f104b Removed unnecessary sram_tb.v file. 2017-10-17 15:51:31 -07:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 10a8531813 Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
Matt Guthaus a9797d12ab Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
Matt Guthaus b2043bef11 Fix small delay difference in unit test 21_hspice_delay_test. 2017-10-05 08:13:53 -07:00
Matt Guthaus 69e44c78d8 Upgrade version to 1.01 2017-10-04 20:18:30 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 7ec20a72c8 Fix old unit test golden result 2017-07-06 14:16:02 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
Matt Guthaus 8a821e13ac Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking. 2017-06-12 15:02:48 -07:00
mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 14:37:15 -07:00
mguthaus a840209c08 Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
Matt Guthaus 93389ac723 Add test to reroute after route fails. Disable GDS route debug info unless verbosity is more than 0. 2017-06-07 10:10:18 -07:00
mguthaus 5960324ca6 Simplify sparse add for grid map. 2017-06-07 09:38:57 -07:00
mguthaus c061b985ba Fix missing map key check in blocked get/set. 2017-06-06 17:12:19 -07:00
Matt Guthaus 8b5e92e582 Merge branch 'master' of github.com:mguthaus/OpenRAM 2017-06-06 11:06:35 -07:00
Matt Guthaus 4e97e385e1 New lib file. Tolerances were off. 2017-06-06 11:06:16 -07:00
Matt Guthaus d67a7149ab Small fixes to last commit. Remove grid pin debug output. Remove extraneous function calls to add grids. 2017-06-05 15:46:50 -07:00
mguthaus 11bb105545 Mark inaccessible off-grid pins as blocked. Improve on-grid pin analysis, but not quite good enough yet. 2017-06-05 14:42:56 -07:00
mguthaus 16063cc9a0 Merge branch 'master' into router 2017-06-05 13:12:51 -07:00
Matt Guthaus 3e2b6e42d4 Merge branch 'router' 2017-06-05 09:08:17 -07:00
Matt Guthaus d20ea65923 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:07:52 -07:00
Matt Guthaus 0acbf43908 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:03:51 -07:00
mguthaus f32912f07c Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
Matt Guthaus b18f0e9905 Moved TODO items to GitHub issues. 2017-05-31 15:47:01 -07:00
Matt Guthaus 384e169b5b Modified unit tests: one for analytical model, one for characterization. 2017-05-31 14:59:22 -07:00
Matt Guthaus 367d4168ad Merge branch 'master' into router 2017-05-31 14:04:31 -07:00
Matt Guthaus d31b1862a3 Improved router debugging and return error if unable to route. 2017-05-31 13:59:49 -07:00
Matt Guthaus 8cc63560f8 Merge branch 'master' into router 2017-05-31 12:09:04 -07:00
Matt Guthaus 424c7b7e64 Made back-annotation and analytical modelling boolean options. Default is false. 2017-05-31 08:12:17 -07:00
Matt Guthaus 46c56863ee Bin Wu fixed unit test to pass with analytical delay option 2017-05-31 08:01:42 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
Matt Guthaus 0fe104af66 Output labels in GDS for debug 2017-05-25 14:18:12 -07:00
Matt Guthaus 7e44d8762e New algorithm for finding pins. Includes off-grid pin computation. 2017-05-25 10:37:24 -07:00
Matt Guthaus dd9b9d73b8 Round pins smaller. 2017-05-24 16:09:43 -07:00
Matt Guthaus 4c0fb2d7d1 Add space around route end rectangles. Separate pin and blockage conversions. 2017-05-24 15:36:30 -07:00
Matt Guthaus 24cfed9fa8 Merge branch 'master' into router 2017-05-24 15:18:06 -07:00
Matt Guthaus 2936038c90 Adding new pin shape conversion using design rules 2017-05-24 15:17:49 -07:00
mguthaus 14b040720b Add some router tests for SCMOS. Not all are there. Found bug in off-grid pin access for one test that is still there. 2017-05-24 13:57:27 -07:00
Matt Guthaus c3769bd375 Added new scmos test with a bigger design. Added error checks for not found label and not found pin shapes. 2017-05-24 10:50:45 -07:00
mguthaus 7ca5c0b34f Added zoom to technology file so labels in each tech are readable size. Made default size. 2017-05-23 16:18:11 -07:00
Matt Guthaus 2e86da4cd1 Add router to the python path 2017-05-23 08:31:23 -07:00
mguthaus 68ce3843fe Debugged and tested route by pin location,layer 2017-05-17 15:58:29 -07:00
Matt Guthaus a1496e70a8 Updated gdsMill with new getter routines for router to get by location. Cleaned up vlsiLayout. 2017-05-17 14:27:14 -07:00
Matt Guthaus b16dd80088 Add checks for valid OPENRAM_HOME and OPENRAM_TECH directories and subdirs 2017-05-12 14:56:31 -07:00
Matt Guthaus cffcd46f6d Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules. 2017-04-26 14:33:03 -07:00
Matt Guthaus 1e8743f5a5 Removed unique id for contacts. Contact/via name, however, must distinguish types of contacts based on layers used. 2017-04-26 10:24:51 -07:00
mguthaus d85f78a54c Fixed format errors 2017-04-24 13:50:19 -07:00
mguthaus 9b86083524 Fixed rotated via bug. May still have a via-to-via spacing problem. 2017-04-24 13:47:56 -07:00
mguthaus 8a185ffc1a Merge branch 'master' into router 2017-04-24 12:17:21 -07:00
Matt Guthaus 21f5444f81 Forgot one more view to comment out 2017-04-24 12:14:19 -07:00
Matt Guthaus e960cbe9d6 Clean up output so that it does not print routing grid debug. 2017-04-24 12:13:01 -07:00
mguthaus bd7958be28 Fixed format test. It was not performing checks due to moving of OPENRAM_HOME. Fixed some tabs and print statements. 2017-04-24 11:55:11 -07:00
Matt Guthaus 9478d6f94d Change width of default text routing grid to display. 2017-04-24 11:33:14 -07:00
Matt Guthaus 388794b1e0 Fix multiple net routing cost reset bug. 2017-04-24 11:28:36 -07:00
Matt Guthaus 96f1eb413e Fixed costs and view grid function so that we have better routes and less expansion. 2017-04-24 10:27:04 -07:00
mguthaus c005960072 Changed DRC and LVS results output database to end in .db instead of .results. Calibre uses file extensions to determine file type. 2017-04-21 14:07:16 -07:00
Matt Guthaus 55ed6212a1 Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually. 2017-04-19 12:41:13 -07:00
mguthaus f51e82e75a Commented unit tests. Added negative coordinate test on test 03. 2017-04-16 08:04:06 -07:00
mguthaus 7cac1a0357 Rename test classes. 2017-04-15 07:49:05 -07:00
mguthaus 2350be8e39 Fixed router test 03. Cleaned up code. 2017-04-14 13:56:09 -07:00
mguthaus b61df7614d Added gds for test 01 2017-04-14 13:19:44 -07:00
mguthaus 76f338e982 Fixed offgrid pins. Added vias to src/dst pins. Added preferred direction routing costs. 2017-04-14 13:18:35 -07:00
Matthew Guthaus 0766db9e11 Rename unit test files according to test. Modify off-grid pins and blockages. Reorganize router code a bit. 2017-04-12 10:59:04 -07:00
Matt Guthaus 1f5841b933 Merge branch 'temp_merge' into router 2017-01-11 12:24:44 -08:00
Matt Guthaus e5c58bf3d5 Merge remote-tracking branch 'origin/master' into HEAD 2017-01-11 12:22:25 -08:00
Matt Guthaus 747af592bd Merge remote-tracking branch 'origin/router' into router 2017-01-11 12:18:42 -08:00
Matt Guthaus e46ff50269 Modified default tech back to freepdk. Config file overrides command line. 2017-01-11 11:47:58 -08:00
Matt Guthaus d46e416c29 Change snap to grid function name 2017-01-11 09:23:17 -08:00
Matt Guthaus a31f87bc72 Merge master branch into router 2017-01-09 14:04:37 -08:00
Matt Guthaus 2d0533a7d5 Merge remote-tracking branch 'bin/merge_hierarchical_decoder' 2016-11-23 17:20:45 -08:00
Matt Guthaus 9356d1771f Merge remote-tracking branch 'bin/move_snap_to_vector_fix1' 2016-11-23 17:19:55 -08:00
Matt Guthaus 841532a52f Change characterizer to be one data structure. Add approximate diff for lib file. 2016-11-23 17:18:48 -08:00
Bin wu a9b7baa206 merge hierarchical_decoder 2x4 and 3x8 routing functions together 2016-11-22 12:23:55 -08:00
Bin wu 8c4b97753a not applying snap_to_grid to all vectors 2016-11-20 11:06:53 -08:00
Bin wu 905f5cf28e Merge branch 'master' of https://github.com/mguthaus/OpenRAM into move_snap_to_vector 2016-11-20 10:48:45 -08:00
Samira Ataei 233acc3fcc Added seprate return for power values of lib. 2016-11-20 11:16:19 -06:00
Matt Guthaus 7969ac2846 Non functioning commit 2016-11-20 08:41:49 -08:00
Samira Ataei d195df682d Added Power results to lib. 
Fixed min_period and min_pulse_width values.
  Updated lib golden files.
 2016-11-19 20:19:16 -06:00
Matt Guthaus 5149ec34f0 Update unit tests with block 2016-11-18 16:17:49 -08:00
Matt Guthaus 2a17856c69 Add src/dest pin block 2016-11-18 16:16:19 -08:00
Matt Guthaus 62237830cd Fix rounding, offsets, and increase halo 2016-11-18 15:49:07 -08:00
Matt Guthaus 7e03eaf41e Shrink blockages to avoid wide metal rules 2016-11-18 15:30:35 -08:00
Matt Guthaus da1df1f580 Fix max track width computation 2016-11-18 15:18:36 -08:00
Matt Guthaus 51d7a673bd Improve debug messages. Remove add_inst for via in wire. 2016-11-18 14:10:30 -08:00
Matt Guthaus 70365a8116 Add double grid snap for centerline wires 2016-11-18 12:57:07 -08:00
Matt Guthaus c802d53a60 Remove view from tests 2016-11-18 11:35:41 -08:00
Matt Guthaus c4d2cb78ef Relative gds file names in tests. 2016-11-18 11:33:03 -08:00
Matt Guthaus 4e505b80dc Convert gds to on grid. Remove view from tests. 2016-11-18 11:30:14 -08:00
Matt Guthaus 396a41733c Added regress script for router 2016-11-18 11:21:39 -08:00
Matt Guthaus 3466162152 Merge branch 'master' into router 2016-11-18 09:20:05 -08:00
Matt Guthaus 710b6d64d7 Fix bug to only see if this path visited a point. 2016-11-18 09:17:59 -08:00
Matt Guthaus ed5700d698 Fix spelling errors. Allow multiple rectangle pin shapes in router. 2016-11-18 08:55:34 -08:00
Matt Guthaus 1c9b5c7372 Document vlsiLayout functions in comments 2016-11-18 08:01:19 -08:00
Matt Guthaus eceb27cad7 Add regress.sh script for convenience 2016-11-18 08:00:34 -08:00
Bin wu a22ba2087b fix the conflicts for merge 2016-11-17 17:19:48 -08:00
Bin wu 0658cc20e6 move snapt_to_grid to a function in vector class 2016-11-17 17:12:48 -08:00
Matt Guthaus c143f62b25 Forgot to add testutils.py 2016-11-17 16:59:22 -08:00
Matt Guthaus e215885b2f Update unit tests. 2016-11-17 16:46:41 -08:00
Matt Guthaus b5b1f1753e Rename tests. Make 4 pin test. 2016-11-17 16:33:38 -08:00
Matt Guthaus 5cef8606b4 Merge branch 'master' into router 2016-11-17 16:11:21 -08:00
Matt Guthaus 19e7100f80 Fix error in metal stack 2016-11-17 16:04:01 -08:00
Matt Guthaus 81ab1f1f82 Change layer order for add_wire 2016-11-17 14:05:50 -08:00
Matt Guthaus 3c7fd924f7 Revert change to horizontal/vertical 2016-11-17 13:51:09 -08:00
Matt Guthaus 717718ed5a Adding checking of rounding and contract path to simplify route wire. 2016-11-17 13:48:27 -08:00
Matt Guthaus 0a9b326f6a Contract path to simplified route 2016-11-17 13:26:03 -08:00
Matt Guthaus aa950c3b21 Fix unit during gds read. Fix blockage and pin rounding bugs. 2016-11-17 11:24:17 -08:00
Matt Guthaus 614ff23e3a Routing multilayer, around blockages. 2016-11-16 16:52:33 -08:00
Matt Guthaus 784bad2e99 Routing multilayer, around blockages. 2016-11-16 16:47:31 -08:00
Matt Guthaus b947989970 Add router data structure, blockage parser, pin parser, initial unit tests 2016-11-16 15:02:07 -08:00
Matt Guthaus d0782df9fe Merge branch 'master' into router 2016-11-15 11:22:30 -08:00
Matt Guthaus 836c7ece73 Merge remote-tracking branch 'origin/master' into router 2016-11-15 10:21:02 -08:00
Matt Guthaus a846132ef8 Merge remote-tracking branch 'bin/clean_unchanged_offset_to_vector' 2016-11-15 10:19:07 -08:00
Matt Guthaus 51e4104624 Modify banner to output temp path 2016-11-15 10:14:04 -08:00
Matt Guthaus a2b7636e58 Modify banner to output temp path 2016-11-15 10:13:57 -08:00
Matt Guthaus 3074349c38 Fix ngspice scnmos results 2016-11-15 10:13:45 -08:00
Matt Guthaus 00b3772b4e Add temp path to test header 2016-11-15 09:55:18 -08:00
Matt Guthaus c33e283283 Fix ngspice results 2016-11-15 09:41:30 -08:00
Matt Guthaus eb57c6e7fd Fix arg parsing order in openram.py 2016-11-15 09:36:15 -08:00
Matt Guthaus d1f6f205c0 No output during level 0 debug. 2016-11-15 09:04:32 -08:00
Matt Guthaus cbc0f7c5d2 run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state. 2016-11-15 09:03:16 -08:00
Matt Guthaus e95e9e8229 Change some debug levels. Fix ngspice test values. ix cwd warning in some tests. 2016-11-15 08:57:06 -08:00
Matt Guthaus 0e2409d836 Fix file compare scope error 2016-11-12 11:16:08 -08:00
Matt Guthaus 392dbc7c56 Moved output of tests 30 to openram_temp 2016-11-12 11:15:55 -08:00
Matt Guthaus 475a5223a7 Moved output of tests 23-25 to openram_temp 2016-11-12 11:15:34 -08:00
Matt Guthaus 7fcce2633f Fix delays in ngspice as they are diff than hspice 2016-11-12 09:28:22 -08:00
Matt Guthaus 2a6b709a41 Merge branch 'master' into router 2016-11-12 08:58:24 -08:00
Matt Guthaus cdb101b377 Sketch new router procedures 2016-11-12 08:57:26 -08:00
Matt Guthaus b82aaa4201 Merge use-temp-dir-pid 2016-11-12 08:55:42 -08:00
Matt Guthaus 096505af14 Merge branch 'use-temp-dir-pid' 2016-11-12 08:49:51 -08:00
Matt Guthaus d85efb772f Temp files were deleted. 2016-11-12 08:49:39 -08:00
Matt Guthaus 7e16bf37df Add code for isdiff to output diff in tests when files mismatch. 2016-11-12 07:56:50 -08:00
Bin wu 072a65a511 add rotate_scale function in vector and use it everywhere 2016-11-11 14:33:19 -08:00
Matt Guthaus 7d0d590879 Don't converge only after a successful measurement. 2016-11-11 14:25:46 -08:00
Matt Guthaus 9ea1a06244 Remove openram_temp at end of openram and unit tests. 2016-11-11 14:05:14 -08:00
Matt Guthaus 5e33781268 Remove control structure from ngspice. Add probe for ngspice too since it doesn't hurt. Unskip delay test. 2016-11-11 13:22:01 -08:00
Matt Guthaus 5211be5ffc No control statements in ngspice 26 2016-11-11 13:10:54 -08:00
Matt Guthaus 33b46b450d No control statements in ngspice 26 2016-11-11 13:09:46 -08:00
Matt Guthaus b9ad65c1de TODO for make characterizer a module 2016-11-11 13:09:26 -08:00
Matt Guthaus 16ea09293c Skip ngspice delay test, too slow 2016-11-11 12:14:13 -08:00
Matt Guthaus 3f879c69c8 Add TODO to convert lib to negative edge for data 2016-11-11 10:04:27 -08:00
Matt Guthaus 07efb52ca9 Lower debug level of relative compare since it's only in unit tests 2016-11-11 10:04:09 -08:00
Matt Guthaus 1356e5142d Add print of values if tests fail. Modify some ngspice tests to pass withcorrect results. 2016-11-11 09:41:43 -08:00
Bin wu 7bae37c026 apply vector to hierchay_layout and geometry and contact 2016-11-10 17:28:06 -08:00
Matt Guthaus c318a7d1bb Check if spice preferred version was found before fallback 2016-11-10 11:44:48 -08:00
Matt Guthaus f3f2171f89 Add both ngspice and hspice timing tests. Add hidden option to force to a version. Otherwise, default to either version if found. 2016-11-10 11:33:10 -08:00
Matt Guthaus 992d091a8b Change step resolution in setup_hold to 5p to avoid convergence problems with ngspice. 2016-11-10 11:07:52 -08:00
Matt Guthaus 868f97caaa Add optimize inverter TODO 2016-11-10 11:07:14 -08:00
Matt Guthaus 46fceba692 More debug messages 2016-11-10 08:55:11 -08:00
Matt Guthaus e017f3f4ca Add better info messages. Convert subprocess to a shell command. 2016-11-10 08:36:28 -08:00
Matt Guthaus 7b90b9a0e6 Try alternative spice if not found. 2016-11-10 08:18:52 -08:00
Matt Guthaus d7afb27322 Break subprocess call into arg list. 2016-11-10 07:27:38 -08:00
Matt Guthaus 342de4e384 Merge branch 'master' of github.com:mguthaus/OpenRAM 2016-11-09 12:21:07 -08:00
Matt Guthaus e1c3d77a5d Removed import cell since cell is removed from simplified txt file 2016-11-09 12:20:52 -08:00
Matt Guthaus 7a23550ae0 Improve error messages on misconfiguration of environment variables. 2016-11-09 12:00:16 -08:00
Matt Guthaus 1fdb0ba5fc Update TODO list 2016-11-09 11:38:36 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00