mirror of https://github.com/VLSIDA/OpenRAM.git
Fix ngspice results
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@ -51,10 +51,10 @@ class timing_sram_test(unittest.TestCase):
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data = d.analyze(probe_address, probe_data)
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if OPTS.tech_name == "freepdk45":
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self.assertTrue(isclose(data['delay1'],0.01333683)) # diff than hspice
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self.assertTrue(isclose(data['delay0'],0.23396480000000003)) # diff than hspice
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self.assertTrue(isclose(data['min_period1'],0.079193115234375)) # diff than hspice
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self.assertTrue(isclose(data['min_period0'],0.260162353515625)) # diff than hspice
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self.assertTrue(isclose(data['delay1'],0.013649)) # diff than hspice
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self.assertTrue(isclose(data['delay0'],0.22893)) # diff than hspice
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self.assertTrue(isclose(data['min_period1'],0.078582763671875)) # diff than hspice
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self.assertTrue(isclose(data['min_period0'],0.25543212890625)) # diff than hspice
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elif OPTS.tech_name == "scn3me_subm":
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self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice
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self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice
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