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Merge update master and dev.

This commit is contained in:
Matt Guthaus 2017-12-18 08:13:59 -08:00
parent 819e249526 ed4ca62dbf
commit 317f2d1293
5 changed files with 49 additions and 49 deletions
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22
compiler/tests/21_hspice_delay_test.py
View File

@ -61,15 +61,15 @@ class timing_sram_test(unittest.TestCase):
'slew0': [0.0265264],
'slew1': [0.0195507]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 4.443,
'read0_power': 4.4712,
'write0_power': 3.0032,
'delay1': [0.8596608],
'delay0': [1.9534000000000002],
'min_period': 5.625,
'write1_power': 2.8086,
'slew0': [1.2982],
'slew1': [0.9909933]}
golden_data = {'read1_power': 4.3678,
'read0_power': 4.3914,
'write0_power': 2.9394,
'delay1': [0.8901521],
'delay0': [2.001],
'min_period': 5.781,
'write1_power': 2.7163,
'slew0': [1.3044000000000002],
'slew1': [0.9904079]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
@ -78,9 +78,9 @@ class timing_sram_test(unittest.TestCase):
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.10))
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.15))
else:
self.assertTrue(isclose(data[k],golden_data[k],0.10))
self.assertTrue(isclose(data[k],golden_data[k],0.15))
# reset these options

4
compiler/tests/21_hspice_setuphold_test.py
View File

@ -54,9 +54,9 @@ class timing_setup_test(unittest.TestCase):
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.10))
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.15))
else:
self.assertTrue(isclose(data[k],golden_data[k],0.10))
self.assertTrue(isclose(data[k],golden_data[k],0.15))
OPTS.check_lvsdrc = True
OPTS.analytical_delay = True

36
compiler/tests/21_ngspice_delay_test.py
View File

@ -47,25 +47,25 @@ class timing_sram_test(unittest.TestCase):
slews = [tech.spice["rise_time"]*2]
data = d.analyze(probe_address, probe_data,slews,loads)
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.02813208,
'read0_power': 0.02856409,
'write0_power': 0.02578581,
'delay1': [0.050279449999999996],
'delay0': [0.1417553],
golden_data = {'read1_power': 0.026660760000000002,
'read0_power': 0.02711731,
'write0_power': 0.02501428,
'delay1': [0.04867702],
'delay0': [0.1423633],
'min_period': 0.332,
'write1_power': 0.02516402,
'slew0': [0.02729188],
'slew1': [0.02057544]}
'write1_power': 0.024162890000000003,
'slew0': [0.02733451],
'slew1': [0.02121624]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 4.324345,
'read0_power': 4.168978,
'write0_power': 2.828746,
'delay1': [0.8929376],
'delay0': [2.01039],
golden_data = {'read1_power': 4.250786000000001,
'read0_power': 4.093461,
'write0_power': 2.762675,
'delay1': [0.920068],
'delay0': [2.051821],
'min_period': 6.563,
'write1_power': 2.526374,
'slew0': [1.342036],
'slew1': [1.041426]}
'write1_power': 2.4545719999999998,
'slew0': [1.342015],
'slew1': [1.040868]}
else:
self.assertTrue(False) # other techs fail
@ -75,9 +75,9 @@ class timing_sram_test(unittest.TestCase):
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.10))
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.15))
else:
self.assertTrue(isclose(data[k],golden_data[k]),0.10)
self.assertTrue(isclose(data[k],golden_data[k],0.15))
# reset these options
OPTS.check_lvsdrc = True

4
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -55,9 +55,9 @@ class timing_setup_test(unittest.TestCase):
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.10))
self.assertTrue(isclose(data[k][i],golden_data[k][i],0.15))
else:
self.assertTrue(isclose(data[k],golden_data[k],0.10))
self.assertTrue(isclose(data[k],golden_data[k],0.15))
# reset these options
OPTS.check_lvsdrc = True

32
compiler/tests/golden/sram_2_16_1_scn3me_subm.lib
View File

@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("3.3427");
values("3.1581");
}
fall_power(scalar){
values("3.6867");
values("3.4945");
}
}
timing(){
@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("5.2453");
values("5.0577");
}
fall_power(scalar){
values("5.2708");
values("5.0831");
}
}
timing(){
@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.509, 0.592, 1.265",\
"0.512, 0.594, 1.271",\
"0.561, 0.641, 1.317");
values("0.542, 0.626, 1.298",\
"0.544, 0.627, 1.304",\
"0.594, 0.674, 1.35");
}
cell_fall(CELL_TABLE) {
values("1.449, 1.549, 2.511",\
"1.454, 1.554, 2.518",\
"1.504, 1.606, 2.568");
values("1.535, 1.637, 2.604",\
"1.54, 1.641, 2.612",\
"1.59, 1.693, 2.662");
}
rise_transition(CELL_TABLE) {
values("0.19, 0.335, 1.887",\
"0.191, 0.336, 1.886",\
"0.193, 0.339, 1.886");
values("0.191, 0.337, 1.883",\
"0.193, 0.338, 1.885",\
"0.195, 0.341, 1.884");
}
fall_transition(CELL_TABLE) {
values("0.282, 0.465, 2.464",\
"0.283, 0.465, 2.463",\
"0.282, 0.465, 2.455");
values("0.252, 0.446, 2.468",\
"0.253, 0.448, 2.448",\
"0.253, 0.447, 2.454");
}
}
}