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RBL width is max of delay chain or bitcell load.

This commit is contained in:
Matt Guthaus 2018-03-05 10:23:13 -08:00
parent 98fb1173df
commit 0c203c1c7e
1 changed files with 2 additions and 1 deletions
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3
compiler/modules/replica_bitline.py
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@ -70,7 +70,8 @@ class replica_bitline(design.design):
self.rbl_offset = self.bitcell_offset
self.height = self.rbl_offset.y + self.rbl.height + self.m2_pitch
self.height = max(self.rbl_offset.y + self.rbl.height + self.m2_pitch,
self.delay_chain_offset.y + self.delay_chain.width + self.m2_pitch)
self.width = self.rbl_offset.x + self.bitcell.width