changed pbitcell_array tests in regards to addition of read/write ports in pbitcell

This commit is contained in:
Michael Timothy Grimes 2018-05-10 09:40:43 -07:00
parent 7af95e4723
commit 3971835f24
2 changed files with 36 additions and 3 deletions

View File

@ -48,15 +48,44 @@ class bitcell(design.design):
def list_row_pins(self):
# Creates a list of row pins
row_pins = ["WL"]
row_pins = ["wl"]
return row_pins
def list_read_row_pins(self):
# Creates a list of row pins
row_pins = ["wl"]
return row_pins
def list_write_row_pins(self):
# Creates a list of row pins
row_pins = ["wl"]
return row_pins
def list_column_pins(self):
# Creates a list of column pins
column_pins = ["BL", "BR"]
column_pins = ["bl", "br"]
return column_pins
def list_read_column_pins(self):
# Creates a list of column pins
column_pins = ["bl"]
return column_pins
def list_read_bar_column_pins(self):
# Creates a list of column pins
column_pins = ["br"]
return column_pins
def list_write_column_pins(self):
# Creates a list of column pins
column_pins = ["bl"]
return column_pins
def list_write_bar_column_pins(self):
# Creates a list of column pins
column_pins = ["br"]
return column_pins
def analytical_power(self, proc, vdd, temp, load):
"""Bitcell power in nW. Only characterizes leakage."""

View File

@ -24,12 +24,16 @@ class array_multiport_test(openram_test):
import bitcell_array
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 2
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
#globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":