luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.

This commit is contained in:
Michael Timothy Grimes 2018-08-18 15:27:07 -07:00
parent e147f807a5
commit 0f8da1510e
4 changed files with 31 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
compiler/modules/precharge_array.py
View File

@ -13,17 +13,15 @@ class precharge_array(design.design):
unique_id = 1
def __init__(self, columns, size=1, BL="bl", BR="br"):
def __init__(self, columns, size=1, bitcell_bl="bl", bitcell_br="br"):
name = "precharge_array_{}".format(precharge_array.unique_id)
precharge_array.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.columns = columns
self.BL = BL
self.BR = BR
self.pc_cell = precharge(name="precharge", size=size, BL=self.BL, BR=self.BR)
self.pc_cell = precharge(name="precharge", size=size, bitcell_bl=bitcell_bl, bitcell_br=bitcell_br)
self.add_mod(self.pc_cell)
self.width = self.columns * self.pc_cell.width
@ -36,8 +34,8 @@ class precharge_array(design.design):
def add_pins(self):
"""Adds pins for spice file"""
for i in range(self.columns):
self.add_pin(self.BL+"[{0}]".format(i))
self.add_pin(self.BR+"[{0}]".format(i))
self.add_pin("bl[{0}]".format(i))
self.add_pin("br[{0}]".format(i))
self.add_pin("en")
self.add_pin("vdd")
@ -70,15 +68,15 @@ class precharge_array(design.design):
offset=offset)
self.local_insts.append(inst)
self.connect_inst([self.BL+"[{0}]".format(i), self.BR+"[{0}]".format(i), "en", "vdd"])
bl_pin = inst.get_pin(self.BL)
self.add_layout_pin(text=self.BL+"[{0}]".format(i),
self.connect_inst(["bl[{0}]".format(i), "br[{0}]".format(i), "en", "vdd"])
bl_pin = inst.get_pin("bl")
self.add_layout_pin(text="bl[{0}]".format(i),
layer="metal2",
offset=bl_pin.ll(),
width=drc["minwidth_metal2"],
height=bl_pin.height())
br_pin = inst.get_pin(self.BR)
self.add_layout_pin(text=self.BR+"[{0}]".format(i),
br_pin = inst.get_pin("br")
self.add_layout_pin(text="br[{0}]".format(i),
layer="metal2",
offset=br_pin.ll(),
width=drc["minwidth_metal2"],

32
compiler/pgates/precharge.py
View File

@ -14,7 +14,7 @@ class precharge(pgate.pgate):
unique_id = 1
def __init__(self, name, size=1, BL="bl", BR="br"):
def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
name = name+"_{}".format(precharge.unique_id)
precharge.unique_id += 1
pgate.pgate.__init__(self, name)
@ -28,15 +28,15 @@ class precharge(pgate.pgate):
self.beta = parameter["beta"]
self.ptx_width = self.beta*parameter["min_tx_size"]
self.width = self.bitcell.width
self.BL = BL
self.BR = BR
self.bitcell_bl = bitcell_bl
self.bitcell_br = bitcell_br
self.add_pins()
self.create_layout()
self.DRC_LVS()
def add_pins(self):
self.add_pin_list([self.BL, self.BR, "en", "vdd"])
self.add_pin_list(["bl", "br", "en", "vdd"])
def create_layout(self):
self.create_ptx()
@ -88,12 +88,12 @@ class precharge(pgate.pgate):
"""Adds both the upper_pmos and lower_pmos to the module"""
# adds the lower pmos to layout
#base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
self.lower_pmos_position = vector(self.bitcell.get_pin(self.BL).lx(),
self.lower_pmos_position = vector(self.bitcell.get_pin(self.bitcell_bl).lx(),
self.pmos.active_offset.y)
self.lower_pmos_inst=self.add_inst(name="lower_pmos",
mod=self.pmos,
offset=self.lower_pmos_position)
self.connect_inst([self.BL, "en", self.BR, "vdd"])
self.connect_inst(["bl", "en", "br", "vdd"])
# adds the upper pmos(s) to layout
ydiff = self.pmos.height + 2*self.m1_space + contact.poly.width
@ -101,13 +101,13 @@ class precharge(pgate.pgate):
self.upper_pmos1_inst=self.add_inst(name="upper_pmos1",
mod=self.pmos,
offset=self.upper_pmos1_pos)
self.connect_inst([self.BL, "en", "vdd", "vdd"])
self.connect_inst(["bl", "en", "vdd", "vdd"])
upper_pmos2_pos = self.upper_pmos1_pos + self.overlap_offset
self.upper_pmos2_inst=self.add_inst(name="upper_pmos2",
mod=self.pmos,
offset=upper_pmos2_pos)
self.connect_inst([self.BR, "en", "vdd", "vdd"])
self.connect_inst(["br", "en", "vdd", "vdd"])
def connect_poly(self):
"""Connects the upper and lower pmos together"""
@ -165,16 +165,16 @@ class precharge(pgate.pgate):
def add_bitlines(self):
"""Adds both bit-line and bit-line-bar to the module"""
# adds the BL on metal 2
offset = vector(self.bitcell.get_pin(self.BL).cx(),0) - vector(0.5 * self.m2_width,0)
self.add_layout_pin(text=self.BL,
offset = vector(self.bitcell.get_pin(self.bitcell_bl).cx(),0) - vector(0.5 * self.m2_width,0)
self.add_layout_pin(text="bl",
layer="metal2",
offset=offset,
width=drc['minwidth_metal2'],
height=self.height)
# adds the BR on metal 2
offset = vector(self.bitcell.get_pin(self.BR).cx(),0) - vector(0.5 * self.m2_width,0)
self.add_layout_pin(text=self.BR,
offset = vector(self.bitcell.get_pin(self.bitcell_br).cx(),0) - vector(0.5 * self.m2_width,0)
self.add_layout_pin(text="br",
layer="metal2",
offset=offset,
width=drc['minwidth_metal2'],
@ -182,10 +182,10 @@ class precharge(pgate.pgate):
def connect_to_bitlines(self):
self.add_bitline_contacts()
self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin(self.BL))
self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin(self.BR))
self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),self.get_pin(self.BL))
self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),self.get_pin(self.BR))
self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin("bl"))
self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin("br"))
self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),self.get_pin("bl"))
self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),self.get_pin("br"))
def add_bitline_contacts(self):

6
compiler/tests/04_precharge_test.py Executable file → Normal file
View File

@ -30,13 +30,13 @@ class precharge_test(openram_test):
OPTS.rw_ports = 2
OPTS.r_ports = 2
OPTS.w_ports = 2
tx = precharge.precharge(name="precharge_driver", size=1, BL="rwbl0", BR="rwbl_bar0")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0")
self.local_check(tx)
tx = precharge.precharge(name="precharge_driver", size=1, BL="wbl0", BR="wbl_bar0")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="wbl0", bitcell_br="wbl_bar0")
self.local_check(tx)
tx = precharge.precharge(name="precharge_driver", size=1, BL="rbl0", BR="rbl_bar0")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rbl0", bitcell_br="rbl_bar0")
self.local_check(tx)
globals.end_openram()

7
compiler/tests/08_precharge_array_test.py
View File

@ -31,17 +31,16 @@ class precharge_test(openram_test):
OPTS.r_ports = 2
OPTS.w_ports = 2
pc = precharge_array.precharge_array(columns=3, BL="rwbl0", BR="rwbl_bar0")
pc = precharge_array.precharge_array(columns=3, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0")
self.local_check(pc)
pc = precharge_array.precharge_array(columns=3, BL="wbl0", BR="wbl_bar0")
pc = precharge_array.precharge_array(columns=3, bitcell_bl="wbl0", bitcell_br="wbl_bar0")
self.local_check(pc)
pc = precharge_array.precharge_array(columns=3, BL="rbl0", BR="rbl_bar0")
pc = precharge_array.precharge_array(columns=3, bitcell_bl="rbl0", bitcell_br="rbl_bar0")
self.local_check(pc)
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":