mirror of https://github.com/VLSIDA/OpenRAM.git
syntax corrections to pbitcell and modifying transistor sizes
This commit is contained in:
Michael Timothy Grimes
parent
7f46a0dead
commit
7d3f7eefac
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@ -12,7 +12,7 @@ class pbitcell(pgate.pgate):
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This module implements a parametrically sized multi-port bitcell
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"""
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def __init__(self, num_write=1, num_read=1):
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def __init__(self, num_write=1, num_read=4):
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name = "pbitcell_{0}W_{1}R".format(num_write, num_read)
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pgate.pgate.__init__(self, name)
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debug.info(2, "create a multi-port bitcell with {0} write ports and {1} read ports".format(num_write, num_read))
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@ -35,9 +35,9 @@ class pbitcell(pgate.pgate):
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self.add_pin("rbl_bar{}".format(k))
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for k in range(self.num_write):
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self.add_pin("wrow{}".format(k))
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self.add_pin("wwl{}".format(k))
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for k in range(self.num_read):
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self.add_pin("rrow{}".format(k))
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self.add_pin("rwl{}".format(k))
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self.add_pin("vdd")
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self.add_pin("gnd")
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@ -61,7 +61,7 @@ class pbitcell(pgate.pgate):
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""" Calculate transistor sizes """
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# if there are no read ports then write transistors are being used as read/write ports, like in a 6T cell
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if(self.num_read == 0):
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inverter_nmos_width = 3*parameter["min_tx_size"]
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inverter_nmos_width = self.num_write*3*parameter["min_tx_size"]
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inverter_pmos_width = parameter["min_tx_size"]
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write_nmos_width = 1.5*parameter["min_tx_size"]
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read_nmos_width = parameter["min_tx_size"] # read transistor not necessary but included as to not generate errors in the code when referenced
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@ -146,7 +146,7 @@ class pbitcell(pgate.pgate):
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self.rightmost_xpos = -self.leftmost_xpos
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# bottommost position = gnd height + wrow height + rrow height + space needed between tiled bitcells
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# bottommost position = gnd height + wwl height + rwl height + space needed between tiled bitcells
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array_tiling_offset = 0.5*drc["minwidth_metal2"]
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self.botmost_ypos = -self.rail_tile_height \
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- self.num_write*self.rowline_tile_height \
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@ -265,7 +265,7 @@ class pbitcell(pgate.pgate):
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def add_write_ports(self):
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"""
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Adds write ports to the bit cell. A single transistor acts as the write port.
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A write is enabled by setting a Write-Rowline (WROW) high, subsequently turning on the transistor.
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A write is enabled by setting a Write-Rowline (WWL) high, subsequently turning on the transistor.
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The transistor is connected between a Write-Bitline (WBL) and the storage component of the cell (Q).
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Driving WBL high or low sets the value of the cell.
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This is a differential design, so each write port has a mirrored port that connects WBL_bar to Q_bar.
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@ -278,7 +278,7 @@ class pbitcell(pgate.pgate):
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# define write transistor variables as empty arrays based on the number of write ports
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self.write_nmos_left = [None] * self.num_write
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self.write_nmos_right = [None] * self.num_write
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self.wrow_positions = [None] * self.num_write
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self.wwl_positions = [None] * self.num_write
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self.wbl_positions = [None] * self.num_write
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self.wbl_bar_positions = [None] * self.num_write
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@ -299,23 +299,23 @@ class pbitcell(pgate.pgate):
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mod=self.write_nmos,
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offset=[left_write_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["Q", "wrow{}".format(k), "wbl{}".format(k), "gnd"])
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self.connect_inst(["Q", "wwl{}".format(k), "wbl{}".format(k), "gnd"])
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self.write_nmos_right[k] = self.add_inst(name="write_nmos_right{}".format(k),
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mod=self.write_nmos,
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offset=[right_write_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["Q_bar", "wrow{}".format(k), "wbl_bar{}".format(k), "gnd"])
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self.connect_inst(["Q_bar", "wwl{}".format(k), "wbl_bar{}".format(k), "gnd"])
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""" Add WROW lines """
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# calculate WROW position
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wrow_ypos = self.gnd_position.y - (k+1)*self.rowline_tile_height
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self.wrow_positions[k] = vector(self.leftmost_xpos, wrow_ypos)
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""" Add WWL lines """
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# calculate WWL position
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wwl_ypos = self.gnd_position.y - (k+1)*self.rowline_tile_height
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self.wwl_positions[k] = vector(self.leftmost_xpos, wwl_ypos)
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# add pin for WROW
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self.add_layout_pin(text="wrow{}".format(k),
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# add pin for WWL
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self.add_layout_pin(text="wwl{}".format(k),
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layer="metal1",
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offset=self.wrow_positions[k],
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offset=self.wwl_positions[k],
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width=self.width,
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height=contact.m1m2.width)
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@ -346,8 +346,8 @@ class pbitcell(pgate.pgate):
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width=drc["minwidth_metal2"],
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height=self.height)
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""" Gate/WROW connections """
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# add poly-to-meltal2 contacts to connect gate of write transistors to WROW (contact next to gate)
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""" Gate/WWL connections """
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# add poly-to-meltal2 contacts to connect gate of write transistors to WWL (contact next to gate)
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# contact must be placed a metal width below the source pin to avoid drc from routing to the source pins
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contact_xpos = self.write_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width
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contact_ypos = self.write_nmos_left[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height
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@ -374,20 +374,20 @@ class pbitcell(pgate.pgate):
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midR = vector(right_gate_contact.x, self.write_nmos_right[k].get_pin("G").rc().y)
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self.add_path("poly", [self.write_nmos_right[k].get_pin("G").rc(), midR, right_gate_contact], width=contact.poly.width)
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# add metal1-to-metal2 contacts to WROW lines
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left_wrow_contact = vector(left_gate_contact.x, self.wrow_positions[k].y + 0.5*contact.m1m2.width)
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# add metal1-to-metal2 contacts to WWL lines
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left_wwl_contact = vector(left_gate_contact.x, self.wwl_positions[k].y + 0.5*contact.m1m2.width)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=left_wrow_contact,
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offset=left_wwl_contact,
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rotate=90)
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right_wrow_contact = vector(right_gate_contact.x, self.wrow_positions[k].y + 0.5*contact.m1m2.width)
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right_wwl_contact = vector(right_gate_contact.x, self.wwl_positions[k].y + 0.5*contact.m1m2.width)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=right_wrow_contact,
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offset=right_wwl_contact,
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rotate=90)
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# connect write transistor gate contacts to WROW contacts (metal2 path)
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self.add_path("metal2", [left_gate_contact, left_wrow_contact])
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self.add_path("metal2", [right_gate_contact, right_wrow_contact])
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# connect write transistor gate contacts to WWL contacts (metal2 path)
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self.add_path("metal2", [left_gate_contact, left_wwl_contact])
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self.add_path("metal2", [right_gate_contact, right_wwl_contact])
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""" Drain/Storage connections """
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# this path only needs to be drawn once on the last iteration of the loop
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@ -424,9 +424,9 @@ class pbitcell(pgate.pgate):
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"""
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Adds read ports to the bit cell. Two transistors function as a read port.
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The two transistors in the port are denoted as the "read transistor" and the "read-access transistor".
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The read transistor is connected to RROW (gate), RBL (drain), and the read-access transistor (source).
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The read transistor is connected to RWL (gate), RBL (drain), and the read-access transistor (source).
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The read-access transistor is connected to Q_bar (gate), gnd (source), and the read transistor (drain).
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A read is enabled by setting a Read-Rowline (RROW) high, subsequently turning on the read transistor.
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A read is enabled by setting a Read-Rowline (RWL) high, subsequently turning on the read transistor.
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The Read-Bitline (RBL) is precharged to high, and when the value of Q_bar is high, the read-access transistor
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is turned on, creating a connection between RBL and gnd. RBL subsequently discharges allowing for a differential read
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using sense amps. This is a differential design, so each read port has a mirrored port that connects RBL_bar to Q.
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@ -444,7 +444,7 @@ class pbitcell(pgate.pgate):
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self.read_nmos_right = [None] * self.num_read
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self.read_access_nmos_left = [None] * self.num_read
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self.read_access_nmos_right = [None] * self.num_read
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self.rrow_positions = [None] * self.num_read
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self.rwl_positions = [None] * self.num_read
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self.rbl_positions = [None] * self.num_read
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self.rbl_bar_positions = [None] * self.num_read
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@ -463,42 +463,42 @@ class pbitcell(pgate.pgate):
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+ read_rotation_correct
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# add read-access transistors
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self.read_access_nmos_left[k] = self.add_inst(name="read_access_nmos_left",
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self.read_access_nmos_left[k] = self.add_inst(name="read_access_nmos_left{}".format(k),
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mod=self.read_nmos,
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offset=[left_read_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["RA_to_R_left{}".format(k), " Q_bar", "gnd", "gnd"])
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self.read_access_nmos_right[k] = self.add_inst(name="read_access_nmos_right",
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self.read_access_nmos_right[k] = self.add_inst(name="read_access_nmos_right{}".format(k),
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mod=self.read_nmos,
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offset=[right_read_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["RA_to_R_right{}".format(k), "Q", "gnd", "gnd"])
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# add read transistors
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self.read_nmos_left[k] = self.add_inst(name="read_nmos_left",
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self.read_nmos_left[k] = self.add_inst(name="read_nmos_left{}".format(k),
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mod=self.read_nmos,
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offset=[left_read_transistor_xpos,overlap_offset.x],
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rotate=90)
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self.connect_inst(["rbl{}".format(k), "rrow{}".format(k), "RA_to_R_left{}".format(k), "gnd"])
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self.connect_inst(["rbl{}".format(k), "rwl{}".format(k), "RA_to_R_left{}".format(k), "gnd"])
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self.read_nmos_right[k] = self.add_inst(name="read_nmos_right",
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self.read_nmos_right[k] = self.add_inst(name="read_nmos_right{}".format(k),
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mod=self.read_nmos,
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offset=[right_read_transistor_xpos,overlap_offset.x],
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rotate=90)
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self.connect_inst(["rbl_bar{}".format(k), "rrow{}".format(k), "RA_to_R_right{}".format(k), "gnd"])
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self.connect_inst(["rbl_bar{}".format(k), "rwl{}".format(k), "RA_to_R_right{}".format(k), "gnd"])
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""" Add RROW lines """
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# calculate RROW position
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rrow_ypos = self.gnd_position.y \
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""" Add RWL lines """
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# calculate RWL position
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rwl_ypos = self.gnd_position.y \
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- self.num_write*self.rowline_tile_height \
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- (k+1)*self.rowline_tile_height
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self.rrow_positions[k] = vector(self.leftmost_xpos, rrow_ypos)
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self.rwl_positions[k] = vector(self.leftmost_xpos, rwl_ypos)
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# add pin for RROW
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self.add_layout_pin(text="rrow{}".format(k),
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# add pin for RWL
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self.add_layout_pin(text="rwl{}".format(k),
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layer="metal1",
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offset=self.rrow_positions[k],
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offset=self.rwl_positions[k],
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width=self.width,
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height=contact.m1m2.width)
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@ -529,8 +529,8 @@ class pbitcell(pgate.pgate):
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width=drc["minwidth_metal2"],
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height=self.height)
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""" Gate of read transistor / RROW connection """
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# add poly-to-meltal2 contacts to connect gate of read transistors to RROW (contact next to gate)
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""" Gate of read transistor / RWL connection """
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# add poly-to-meltal2 contacts to connect gate of read transistors to RWL (contact next to gate)
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contact_xpos = left_read_transistor_xpos - self.read_nmos.active_height - drc["minwidth_poly"] - 0.5*contact.poly.width
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contact_ypos = self.read_nmos_left[k].get_pin("G").lc().y
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left_gate_contact = vector(contact_xpos, contact_ypos)
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@ -553,20 +553,20 @@ class pbitcell(pgate.pgate):
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self.add_path("poly", [self.read_nmos_left[k].get_pin("G").lc(), left_gate_contact])
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self.add_path("poly", [self.read_nmos_right[k].get_pin("G").rc(), right_gate_contact])
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# add metal1-to-metal2 contacts to RROW lines
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left_rrow_contact = vector(left_gate_contact.x, self.rrow_positions[k].y + 0.5*contact.m1m2.width)
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# add metal1-to-metal2 contacts to RWL lines
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left_rwl_contact = vector(left_gate_contact.x, self.rwl_positions[k].y + 0.5*contact.m1m2.width)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=left_rrow_contact,
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offset=left_rwl_contact,
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rotate=90)
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right_rrow_contact = vector(right_gate_contact.x, self.rrow_positions[k].y + 0.5*contact.m1m2.width)
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right_rwl_contact = vector(right_gate_contact.x, self.rwl_positions[k].y + 0.5*contact.m1m2.width)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=right_rrow_contact,
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offset=right_rwl_contact,
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rotate=90)
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# connect read transistor gate contacts to RROW contacts (metal2 path)
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self.add_path("metal2", [left_gate_contact, left_rrow_contact])
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self.add_path("metal2", [right_gate_contact, right_rrow_contact])
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# connect read transistor gate contacts to RWL contacts (metal2 path)
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self.add_path("metal2", [left_gate_contact, left_rwl_contact])
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self.add_path("metal2", [right_gate_contact, right_rwl_contact])
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""" Source of read-access transistor / GND connection """
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# connect source of read-access transistor to GND (metal1 path)
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@ -723,9 +723,9 @@ class pbitcell(pgate.pgate):
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bitcell_pins.append("rbl{0}[{1}]".format(k,col))
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bitcell_pins.append("rbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_write):
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bitcell_pins.append("wrow{0}[{1}]".format(k,row))
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bitcell_pins.append("wwl{0}[{1}]".format(k,row))
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for k in range(self.num_read):
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bitcell_pins.append("rrow{0}[{1}]".format(k,row))
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bitcell_pins.append("rwl{0}[{1}]".format(k,row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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@ -736,9 +736,9 @@ class pbitcell(pgate.pgate):
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# Creates a list of row pins
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row_pins = []
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for k in range(self.num_write):
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row_pins.append("wrow{0}".format(k))
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row_pins.append("wwl{0}".format(k))
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for k in range(self.num_read):
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row_pins.append("rrow{0}".format(k))
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row_pins.append("rwl{0}".format(k))
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return row_pins
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