Add LVS correspondence points to each bank type

compiler/sram_1bank.py

@@ -192,3 +192,14 @@ class sram_1bank(sram_base):
                 
             
 
+    def add_lvs_correspondence_points(self):
+        """ 
+        This adds some points for easier debugging if LVS goes wrong. 
+        These should probably be turned off by default though, since extraction
+        will show these as ports in the extracted netlist.
+        """
+        
+        for n in self.control_logic_outputs:
+            self.add_label(text=n,
+                           layer="metal3",  
+                           offset=self.control_logic_inst.get_pin(n).center())

compiler/sram_2bank.py

@@ -214,3 +214,20 @@ class sram_2bank(sram_base):
 
 
         
+    def add_lvs_correspondence_points(self):
+        """ 
+        This adds some points for easier debugging if LVS goes wrong. 
+        These should probably be turned off by default though, since extraction
+        will show these as ports in the extracted netlist.
+        """
+        
+        if self.num_banks==1: return
+        
+        for n in self.control_bus_names:
+            self.add_label(text=n,
+                           layer="metal2",  
+                           offset=self.vert_control_bus_positions[n])
+        for n in self.bank_sel_bus_names:
+            self.add_label(text=n,
+                           layer="metal2",  
+                           offset=self.vert_control_bus_positions[n])

compiler/sram_4bank.py

@@ -312,3 +312,20 @@ class sram_4bank(sram_base):
         self.route_bank_supply_rails(left_banks=[0,2], bottom_banks=[2,3])
 
 
+    def add_lvs_correspondence_points(self):
+        """ 
+        This adds some points for easier debugging if LVS goes wrong. 
+        These should probably be turned off by default though, since extraction
+        will show these as ports in the extracted netlist.
+        """
+        
+        if self.num_banks==1: return
+        
+        for n in self.control_bus_names:
+            self.add_label(text=n,
+                           layer="metal2",  
+                           offset=self.vert_control_bus_positions[n])
+        for n in self.bank_sel_bus_names:
+            self.add_label(text=n,
+                           layer="metal2",  
+                           offset=self.vert_control_bus_positions[n])

compiler/sram_base.py

@@ -118,6 +118,7 @@ class sram_base(design):
         """ Layout creation """    
         self.add_modules()
         self.route()
+        self.add_lvs_correspondence_points()
 
     def compute_bus_sizes(self):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
@@ -389,21 +390,6 @@ class sram_base(design):
 
 
         
-    def add_lvs_correspondence_points(self):
-        """ This adds some points for easier debugging if LVS goes wrong. 
-        These should probably be turned off by default though, since extraction
-        will show these as ports in the extracted netlist.
-        """
-        if self.num_banks==1: return
-        
-        for n in self.control_bus_names:
-            self.add_label(text=n,
-                           layer="metal2",  
-                           offset=self.vert_control_bus_positions[n])
-        for n in self.bank_sel_bus_names:
-            self.add_label(text=n,
-                           layer="metal2",  
-                           offset=self.vert_control_bus_positions[n])