mirror of https://github.com/VLSIDA/OpenRAM.git
Refactor openram.py.
This commit is contained in:
Matt Guthaus
parent
54c21f6282
commit
6c89f7965d
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@ -16,13 +16,7 @@ USAGE = "Usage: openram.py [options] <config file>\nUse -h for help.\n"
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# Anonymous object that will be the options
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OPTS = options.options()
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# check that we are not using version 3 and at least 2.7
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major_python_version = sys.version_info.major
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minor_python_version = sys.version_info.minor
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if not (major_python_version == 2 and minor_python_version >= 7):
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debug.error("Python 2.7 is required.",-1)
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def parse_args():
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def parse_args(is_unit_test=True):
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""" Parse the optional arguments for OpenRAM """
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global OPTS
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@ -36,8 +30,6 @@ def parse_args():
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help="Output file(s) location"),
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optparse.make_option("-n", "--nocheck", action="store_false",
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help="Disable inline LVS/DRC checks", dest="check_lvsdrc"),
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optparse.make_option("-q", "--quiet", action="store_false", dest="print_banner",
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help="Don\'t display banner"),
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optparse.make_option("-v", "--verbose", action="count", dest="debug_level",
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help="Increase the verbosity level"),
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optparse.make_option("-t", "--tech", dest="tech_name",
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@ -66,13 +58,19 @@ def parse_args():
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# Alias SCMOS to AMI 0.5um
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if OPTS.tech_name == "scmos":
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OPTS.tech_name = "scn3me_subm"
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# Check that we have a single configuration file as argument.
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OPTS.is_unit_test=is_unit_test
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if not OPTS.is_unit_test and len(args) < 1:
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print(USAGE)
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sys.exit(2)
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return (options, args)
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def print_banner():
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""" Conditionally print the banner to stdout """
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global OPTS
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if not OPTS.print_banner:
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if OPTS.is_unit_test:
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return
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print("|==============================================================================|")
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@ -89,8 +87,17 @@ def print_banner():
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print("|==============================================================================|")
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def check_versions():
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""" check that we are not using version 3 and at least 2.7 """
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major_python_version = sys.version_info.major
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minor_python_version = sys.version_info.minor
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if not (major_python_version == 2 and minor_python_version >= 7):
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debug.error("Python 2.7 is required.",-1)
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def init_openram(config_file):
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"""Initialize the technology, paths, simulators, etc."""
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check_versions()
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debug.info(1,"Initializing OpenRAM...")
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@ -100,6 +107,8 @@ def init_openram(config_file):
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import_tech()
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report_status()
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def get_tool(tool_type, preferences):
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"""
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@ -173,6 +182,7 @@ def read_config(config_file):
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def end_openram():
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""" Clean up openram for a proper exit """
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cleanup_paths()
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@ -270,3 +280,39 @@ def import_tech():
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debug.error("Nonexistent technology_setup_file: {0}.py".format(filename))
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sys.exit(1)
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def print_time(name, now_time, last_time=None):
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if last_time:
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time = round((now_time-last_time).total_seconds(),1)
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else:
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time = now_time
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print("** {0}: {1} seconds".format(name,time))
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return now_time
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def report_status():
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""" Check for valid arguments and report the info about the SRAM being generated """
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# Check if all arguments are integers for bits, size, banks
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if type(OPTS.word_size)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
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if type(OPTS.num_words)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
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if type(OPTS.num_banks)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.num_banks))
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if not OPTS.tech_name:
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debug.error("Tech name must be specified in config file.")
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if (OPTS.output_name == ""):
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OPTS.output_name = "sram_{0}_{1}_{2}_{3}".format(OPTS.word_size,
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OPTS.num_words,
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OPTS.num_banks,
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OPTS.OPTS.tech_name)
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if not OPTS.is_unit_test:
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print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
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print("Technology: {0}".format(OPTS.tech_name))
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print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
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OPTS.num_words,
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OPTS.num_banks))
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if not OPTS.check_lvsdrc:
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print("DRC/LVS/PEX checking is disabled.")
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@ -14,116 +14,39 @@ import sys,os
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import datetime
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import re
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import importlib
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import globals
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from globals import *
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(OPTS, args) = globals.parse_args()
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def print_time(name, now_time, last_time=None):
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if last_time:
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time = round((now_time-last_time).total_seconds(),1)
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else:
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time = now_time
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print("** {0}: {1} seconds".format(name,time))
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return now_time
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(OPTS, args) = parse_args(is_unit_test=False)
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# These depend on arguments, so don't load them until now.
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import debug
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# required positional args for using openram main exe
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if len(args) < 1:
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print(globals.USAGE)
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sys.exit(2)
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# Only print banner here so it's not in unit tests
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print_banner()
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globals.print_banner()
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init_openram(args[0])
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globals.init_openram(args[0])
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# Check if all arguments are integers for bits, size, banks
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if type(OPTS.word_size)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
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if type(OPTS.num_words)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
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if type(OPTS.num_banks)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.num_banks))
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if not OPTS.tech_name:
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debug.error("Tech name must be specified in config file.")
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word_size = OPTS.word_size
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num_words = OPTS.num_words
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num_banks = OPTS.num_banks
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if (OPTS.output_name == ""):
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OPTS.output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,
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num_words,
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num_banks,
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OPTS.tech_name)
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print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
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print("Technology: {0}".format(OPTS.tech_name))
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print("Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks))
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# only start importing modules after we have the config file
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# Start importing design modules after we have the config file
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import verify
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import sram
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# Keep track of running stats
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start_time = datetime.datetime.now()
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last_time = start_time
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print_time("Start",datetime.datetime.now())
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if not OPTS.check_lvsdrc:
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print("DRC/LVS/PEX checking is disabled.")
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print_time("Start",last_time)
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# import SRAM test generation
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s = sram.sram(word_size=word_size,
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num_words=num_words,
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num_banks=num_banks,
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s = sram.sram(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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num_banks=OPTS.num_banks,
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name=OPTS.output_name)
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last_time=print_time("SRAM creation", datetime.datetime.now(), last_time)
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# Output the files for the resulting SRAM
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s.save_output(last_time)
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spname = OPTS.output_path + s.name + ".sp"
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print("SP: Writing to {0}".format(spname))
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s.sp_write(spname)
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last_time=print_time("Spice writing", datetime.datetime.now(), last_time)
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# Output the extracted design
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sram_file = spname
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if OPTS.use_pex:
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sram_file = OPTS.output_path + "temp_pex.sp"
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verify.run_pex(s.name, gdsname, spname, output=sram_file)
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# Characterize the design
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from characterizer import lib
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libname = OPTS.output_path + s.name + ".lib"
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print("LIB: Writing to {0}".format(libname))
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if OPTS.analytical_delay:
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print("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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print("Trimming netlist to speed up characterization.")
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lib.lib(libname,s,sram_file)
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last_time=print_time("Characterization", datetime.datetime.now(), last_time)
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# Write the layout
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gdsname = OPTS.output_path + s.name + ".gds"
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print("GDS: Writing to {0}".format(gdsname))
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s.gds_write(gdsname)
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last_time=print_time("GDS", datetime.datetime.now(), last_time)
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# Create a LEF physical model
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lefname = OPTS.output_path + s.name + ".lef"
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print("LEF: Writing to {0}".format(lefname))
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s.lef_write(lefname)
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last_time=print_time("LEF", datetime.datetime.now(), last_time)
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# Write a verilog model
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vname = OPTS.output_path + s.name + ".v"
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print("Verilog: Writing to {0}".format(vname))
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s.verilog_write(vname)
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last_time=print_time("Verilog", datetime.datetime.now(), last_time)
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globals.end_openram()
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# Delete temp files etc.
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end_openram()
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print_time("End",datetime.datetime.now(), start_time)
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@ -8,7 +8,7 @@ from bank import bank
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import datetime
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import getpass
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from vector import vector
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from globals import OPTS
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from globals import OPTS, print_time
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class sram(design.design):
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@ -1009,3 +1009,50 @@ class sram(design.design):
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def analytical_delay(self,slew,load):
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""" LH and HL are the same in analytical model. """
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return self.bank.analytical_delay(slew,load)
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def save_output(self, last_time):
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""" Save all the output files while reporting time to do it as well. """
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spname = OPTS.output_path + self.name + ".sp"
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print("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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last_time=print_time("Spice writing", datetime.datetime.now(), last_time)
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# Output the extracted design
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sram_file = spname
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if OPTS.use_pex:
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sram_file = OPTS.output_path + "temp_pex.sp"
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verify.run_pex(self.name, gdsname, spname, output=sram_file)
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# Characterize the design
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from characterizer import lib
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libname = OPTS.output_path + self.name + ".lib"
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print("LIB: Writing to {0}".format(libname))
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if OPTS.analytical_delay:
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print("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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print("Trimming netlist to speed up characterization.")
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lib.lib(libname,self,sram_file)
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last_time=print_time("Characterization", datetime.datetime.now(), last_time)
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# Write the layout
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gdsname = OPTS.output_path + self.name + ".gds"
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print("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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last_time=print_time("GDS", datetime.datetime.now(), last_time)
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# Create a LEF physical model
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lefname = OPTS.output_path + self.name + ".lef"
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print("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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last_time=print_time("LEF", datetime.datetime.now(), last_time)
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# Write a verilog model
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vname = OPTS.output_path + self.name + ".v"
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print("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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last_time=print_time("Verilog", datetime.datetime.now(), last_time)
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