mirror of https://github.com/VLSIDA/OpenRAM.git
Modified unit tests: one for analytical model, one for characterization.
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@ -25,32 +25,24 @@ class lib_test(unittest.TestCase):
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import lib
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debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
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total_size = 1024
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for word_size in [1,2,4,8,16,32,64]:
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num_words = total_size/word_size# OPTS.config.num_words
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s = sram.sram(word_size=word_size,
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num_words=num_words,
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num_banks=OPTS.config.num_banks,
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name="sram_2_16_1_{0}".format(OPTS.tech_name))
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delay = s.analytical_model(0.1)
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s = sram.sram(word_size=2,
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num_words=OPTS.config.num_words,
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num_banks=OPTS.config.num_banks,
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name="sram_2_16_1_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = True
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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filename = s.name + ".lib"
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filename = s.name + "_analytical.lib"
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libname = OPTS.openram_temp + filename
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use_model = True
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lib.lib(libname,s,tempspice,use_model)
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lib.lib(libname,s,tempspice,use_model=True)
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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# Randomly decided 10% difference between spice simulators is ok.
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if use_model != True:
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self.assertEqual(isapproxdiff(libname,golden,0.10),True)
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# Randomly decided 1% difference between spice simulators is ok.
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self.assertEqual(isapproxdiff(libname,golden,0.01),True)
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os.system("rm {0}".format(libname))
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@ -34,10 +34,7 @@ class lib_test(unittest.TestCase):
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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if OPTS.analytical_delay == True:
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filename = s.name + "_analytical.lib"
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else:
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filename = s.name + ".lib"
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filename = s.name + ".lib"
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libname = OPTS.openram_temp + filename
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lib.lib(libname,s,tempspice)
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