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OpenRAM
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  • da3cdbe4fa
         Merge 6c7c6a9fba into ed369f1af4 Felix Schneider 2026-06-27 11:52:46 -0700
  • c4e94f25d3
         Merge pull request #297 from Aurora7913/close-filehandles dev Matt Guthaus 2026-06-27 14:52:18 -0400
  • ed369f1af4 change spare cols routing from channel to normal routing to avoid short circuits stable Jesse Cirimelli-Low 2026-06-24 14:04:21 -0700
  • 734be5403e fix naming for spare cols Jesse Cirimelli-Low 2026-06-24 11:27:28 -0700
  • 448f0ce488
         close version file after reading Maarten Boersma 2026-06-24 10:15:15 +0200
  • d0fb2149d9
         Because the logfile handle is opened everytime before writing a message, we should also close it after writing a line Maarten Boersma 2026-06-24 10:06:20 +0200
  • 6d852b0930
         Merge aa2cf88870 into e16d9eb0b4 Mik Igor 2026-05-24 17:15:53 +0800
  • 747eb203db
         Merge 21868f9de7 into d309a25c4c Marti Alonso 2026-05-24 17:15:47 +0800
  • d309a25c4c update wmask test to work for sky130 single port Jesse Cirimelli-Low 2026-05-14 19:46:42 -0700
  • 8c4f4ef27f when routing between the wordline drivers and the wordline pins of the crba, midden metal in the jog to resolve drc violations if needed Jesse Cirimelli-Low 2026-05-14 19:25:27 -0700
  • 541b744e82 create separate nand cells for user drc sky130 cell Jesse Cirimelli-Low 2026-05-14 16:21:29 -0700
  • cc9f294992 use more conservative metric for metal mergeing in array to power rail routing Jesse Cirimelli-Low 2026-05-14 11:18:31 -0700
  • 269386e6b8 clean up code Jesse Cirimelli-Low 2026-05-14 02:10:44 -0700
  • c3da65c33c sky130 dp bank passing Jesse Cirimelli-Low 2026-05-14 01:58:41 -0700
  • 5222224936 route supplies from endcaps to power ring Jesse Cirimelli-Low 2026-05-13 16:45:52 -0700
  • afca50c20b power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors Jesse Cirimelli-Low 2026-05-13 12:35:08 -0700
  • 34b317ce7d remove debug print statements Jesse Cirimelli-Low 2026-05-11 16:05:20 -0700
  • 9fcf61f031 merge in array generation branch Jesse Cirimelli-Low 2026-05-11 13:09:52 -0700
  • e16d9eb0b4 make sky130-install now correctly merges with privded cells Jesse Cirimelli-Low 2026-05-04 17:32:07 -0700
  • 2f8f9bc2e3 use python venv so we can still run make library Jesse Cirimelli-Low 2026-05-04 16:56:27 -0700
  • 91d0eb1d2c use python venv with nix Jesse Cirimelli-Low 2026-05-04 16:39:33 -0700
  • 45e58838d6 fix ciel repo Jesse Cirimelli-Low 2026-05-04 16:25:26 -0700
  • c1e93ce686 add ciel to nix flake for pdk managementment Jesse Cirimelli-Low 2026-05-04 13:01:52 -0700
  • cbd2bd7c2e switch from conda to nix for tooling Jesse Cirimelli-Low 2026-04-30 12:00:56 -0700
  • c864427734 make contacts perpendicular to power rails to avoid drc violations array_gen-to-dev Jesse Cirimelli-Low 2026-05-07 15:03:53 -0700
  • c3987f2537 change power ring spacing from magic numbers to drc based Jesse Cirimelli-Low 2026-05-07 14:18:58 -0700
  • e7829cf641 allow tech file to specify connection to power rail per net Jesse Cirimelli-Low 2026-05-06 10:42:02 -0700
  • 541d4ff572 parameterize how power ring is connected to crba Jesse Cirimelli-Low 2026-05-06 09:50:56 -0700
  • 28fef79202 make sky130-install now correctly merges with privded cells Jesse Cirimelli-Low 2026-05-04 17:32:07 -0700
  • 797664c343 update sky130 cell paths Jesse Cirimelli-Low 2026-05-04 17:15:49 -0700
  • c089ff0e78 update git ignore so we can track just our sky130 cells Jesse Cirimelli-Low 2026-05-04 17:07:33 -0700
  • 88cf3ae401 use python venv so we can still run make library Jesse Cirimelli-Low 2026-05-04 16:56:27 -0700
  • 5bd5293b4e use python venv with nix Jesse Cirimelli-Low 2026-05-04 16:39:33 -0700
  • 07b33b3dfd fix ciel repo Jesse Cirimelli-Low 2026-05-04 16:25:26 -0700
  • 4e93ba0424 add ciel to nix flake for pdk managementment Jesse Cirimelli-Low 2026-05-04 13:01:52 -0700
  • 03c5a58758 add sp non cypress bitcells Jesse Cirimelli-Low 2026-05-04 12:47:00 -0700
  • e4a895ecb0 fix verbosity level Jesse Cirimelli-Low 2026-04-30 13:02:03 -0700
  • a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev Jesse Cirimelli-Low 2026-04-30 12:43:19 -0700
  • ddac4254ec switch from conda to nix for tooling Jesse Cirimelli-Low 2026-04-30 12:00:56 -0700
  • 2780fda35c all sky130 crba passing Jesse Cirimelli-Low 2026-04-28 23:22:40 -0700
  • 88241ca685 add fix for cypress sp wls Jesse Cirimelli-Low 2026-04-28 17:19:54 -0700
  • 5077282180 count wordlines from bottom going up Jesse Cirimelli-Low 2026-04-28 14:04:42 -0700
  • c7f3ac33cd sky130 cypress dp working with offset relative to crba Jesse Cirimelli-Low 2026-04-27 17:24:13 -0700
  • 3e569feebf Merge branch 'dev' into array_gen Jesse Cirimelli-Low 2026-04-22 01:38:59 -0700
  • cb7f117daa squash commits Jesse Cirimelli-Low 2026-04-22 01:33:47 -0700
  • bc4347eadc
         Merge d4dc7e94a2 into f2db9fe2de K.Makise 2026-04-21 19:28:07 +0530
  • f2db9fe2de
         Merge pull request #291 from goobber-gawber/modernize2 Matt Guthaus 2026-04-17 07:25:26 -0700
  • 5cd43442b8 compiler: gdsMill: Modernize codebase. Gabriel Wicki 2026-04-17 13:14:03 +0200
  • 5fd548582f bump cell lib version for dual port fixes Jesse Cirimelli-Low 2026-04-14 15:10:30 -0700
  • 515591a422 dual port rba lvs clean again with cell library changes Jesse Cirimelli-Low 2026-04-14 14:48:26 -0700
  • 9274fbd4f2 Merge branch 'stable' into dev Matthew Guthaus 2026-04-08 11:26:03 -0700
  • 449781d239 Revert "Revert "Update defunct code"" Matthew Guthaus 2026-04-08 11:25:48 -0700
  • 148a5807e2
         Merge pull request #290 from VLSIDA/revert-289-update-defunct-code Matt Guthaus 2026-04-08 11:19:40 -0700
  • d142b906ee
         Revert "Update defunct code" revert-289-update-defunct-code Matt Guthaus 2026-04-08 11:19:03 -0700
  • 29e8521ea3
         Merge pull request #289 from goobber-gawber/update-defunct-code Matt Guthaus 2026-04-08 11:10:28 -0700
  • e01e6a567d compiler: gdsMill: Modernize codebase. Gabriel Wicki 2026-03-31 22:44:21 +0200
  • 26e11044db compiler: multibank: Fix syntax error. Gabriel Wicki 2026-03-31 22:28:10 +0200
  • b6d98c44d5 singleport cba passing on both tech files Jesse Cirimelli-Low 2026-03-17 14:50:43 -0700
  • ffcbd51019 technology switching working Jesse Cirimelli-Low 2026-03-17 11:44:20 -0700
  • ab33017fe2
         Merge pull request #282 from ruhai-lin/stable Jesse Cirimelli-Low 2026-03-12 10:47:23 -0700
  • 6d14626a75 Fix address bit ordering in sky130 1rw characterization rlin50 2026-02-23 15:32:08 -0800
  • ec28bc6dfd Fix sky130 1rw LVS mismatch by correcting col_cap pin order rlin50 2026-02-22 22:11:35 -0800
  • c99b134deb
         Merge pull request #280 from Aurora7913/issue279 Matt Guthaus 2026-01-16 06:24:55 -0800
  • e32f3164e4
         fix typo Maarten Boersma 2026-01-16 14:58:41 +0100
  • 7382ea7dda
         fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene Maarten Boersma 2026-01-16 13:40:05 +0100
  • 53d53ec271 checkpoint from tt submission Jesse Cirimelli-Low 2026-01-14 12:08:26 -0800
  • ce5595adf1
         Merge pull request #275 from vikashpatel24/dev Matt Guthaus 2025-10-17 09:46:49 -0700
  • b9bb6898af Fix for Missing lef_rom_interconnect in tech.py Vikash Patel 2025-10-17 14:40:03 +0530
  • 5a74605117 single port fixes Jesse Cirimelli-Low 2025-09-12 11:25:03 -0700
  • 21868f9de7 Consider spare columns when building liberty file Marti Alonso 2025-08-15 23:48:31 +0000
  • ea15a81443
         Merge pull request #270 from hpretl/stable Matt Guthaus 2025-06-26 13:15:50 -0700
  • 9492349d7a Bump version Harald Pretl 2025-06-26 21:21:13 +0200
  • 01686a2005 Switch from `volare` to `ciel` Harald Pretl 2025-06-26 21:21:06 +0200
  • e63f70da5e Update README by removing slack and email group. Update website. Matthew Guthaus 2025-04-01 10:44:49 -0700
  • 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next Jesse Cirimelli-Low 2025-03-06 02:05:43 -0800
  • f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen Jesse Cirimelli-Low 2025-02-24 23:26:28 -0800
  • d4dc7e94a2 remove gitlab-ci FriedrichWu 2025-02-12 09:51:12 +0100
  • 2ff7833e3b
         Merge pull request #1 from FriedrichWu/dev_supply_fix K.Makise 2025-02-09 10:06:15 +0100
  • a0ff83c00a solve overlap of wmask in channel router FriedrichWu 2024-12-23 23:44:21 +0100
  • 48a7065b31 make channel router better FriedrichWu 2024-12-23 19:38:42 +0100
  • 691f7a989e speed up constructive approach in 1rw-only FriedrichWu 2024-12-23 17:19:19 +0100
  • 70ed2a506e deleting spacing, add ci test, fixing merge error FriedrichWu 2024-12-22 12:14:57 +0100
  • 74cab87782 add tech fix FriedrichWu 2024-12-21 18:57:06 +0100
  • 474a240f38 move apporach select to options.py FriedrichWu 2024-12-21 18:22:06 +0100
  • bda3adf9f9 more stable FriedrichWu 2024-12-16 00:13:40 +0100
  • 4fe635a05f add route_outside, remove unused methods FriedrichWu 2024-11-20 16:24:26 +0100
  • 86588619fd first commt FriedrichWu 2024-11-17 10:35:01 +0100
  • 8104a42f0e
         Update artifact action Jesse Cirimelli-Low 2024-11-13 22:45:31 -0800
  • bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev mrg 2024-11-12 09:49:00 -0800
  • 3184e1d0e4 Merge branch 'add-doc' of github.com:FriedrichWu/OpenRAM into dev mrg 2024-11-12 09:47:57 -0800
  • f56460bb94 make code clean FriedrichWu 2024-11-12 17:02:02 +0100
  • 7ec407314a add documentation FriedrichWu 2024-11-11 16:18:45 +0100
  • 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard Tristan Robitaille 2024-11-10 14:31:21 +0100
  • 1f1f064036 fix clk csb overlap problem FriedrichWu 2024-10-31 09:44:11 +0100
  • 434063656f fix bugs in channel routing, which will add strange shape in m2 at dff pins FriedrichWu 2024-10-31 09:43:34 +0100
  • 61f5ff6ec4 updata io_pin_placer FriedrichWu 2024-10-30 13:24:53 +0100
  • ee6be23cfa first comment FriedrichWu 2024-09-17 11:54:30 +0200
  • 20e454925a add io placer FriedrichWu 2024-09-05 10:14:00 +0200
  • 6743049d44 clean version FriedrichWu 2024-09-05 10:08:59 +0200
  • 0ae194f17c Simple version fix FriedrichWu 2024-08-20 09:28:48 +0200