mirror of https://github.com/VLSIDA/OpenRAM.git
Route precharge_array vdd in M3
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parent
f9916f9f43
commit
a772217172
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@ -37,28 +37,34 @@ class precharge_array(design.design):
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def create_layout(self):
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self.add_insts()
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=self.pc_cell.get_pin("vdd").ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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self.add_layout_pins()
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def add_layout_pins(self):
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self.add_layout_pin(text="en",
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layer="metal1",
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offset=self.pc_cell.get_pin("en").ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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for inst in self.local_insts:
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self.copy_layout_pin(inst, "vdd")
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def add_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.local_insts = []
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for i in range(self.columns):
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name = "pre_column_{0}".format(i)
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offset = vector(self.pc_cell.width * i, 0)
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inst=self.add_inst(name=name,
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mod=self.pc_cell,
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offset=offset)
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inst = self.add_inst(name=name,
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mod=self.pc_cell,
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offset=offset)
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self.local_insts.append(inst)
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self.connect_inst(["bl[{0}]".format(i), "br[{0}]".format(i), "en", "vdd"])
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bl_pin = inst.get_pin("bl")
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self.add_layout_pin(text="bl[{0}]".format(i),
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layer="metal2",
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@ -71,6 +77,4 @@ class precharge_array(design.design):
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offset=br_pin.ll(),
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width=drc["minwidth_metal2"],
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height=bl_pin.height())
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self.connect_inst(["bl[{0}]".format(i), "br[{0}]".format(i),
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"en", "vdd"])
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