mirror of https://github.com/VLSIDA/OpenRAM.git
Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.
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@ -3,6 +3,9 @@ num_words = 128
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num_banks = 1
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tech_name = "freepdk45"
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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output_path = "temp"
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output_name = "sram_2_16_1_freepdk45"
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@ -3,8 +3,9 @@ num_words = 16
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num_banks = 1
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tech_name = "scn3me_subm"
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process_corners = ["TT"]
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supply_voltages = [ 5.0 ]
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temperatures = [ 25.0 ]
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temperatures = [ 25 ]
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output_path = "temp"
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@ -39,7 +39,7 @@ class options(optparse.Values):
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# Define the output file paths
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output_path = "."
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# Define the output file base name
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output_name = "sram"
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output_name = ""
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# Use analytical delay models by default rather than (slow) characterization
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analytical_delay = True
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# Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
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@ -0,0 +1,9 @@
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word_size = 32
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num_words = 1024
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num_banks = 1
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tech_name = "freepdk45"
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output_path = "sram_1rw_32b_1k_freepdk45"
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