mirror of https://github.com/VLSIDA/OpenRAM.git
Fix delay test unit test results.
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85595b0f6f
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0e0516c4a6
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@ -60,16 +60,16 @@ class timing_sram_test(openram_test):
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'delay_hl': [0.3929995],
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'slew_lh': [0.02160862]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'leakage_power': 0.00142014,
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'delay_lh': [0.8018421],
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'read0_power': [11.44908],
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'read1_power': [11.416549999999999],
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'write1_power': [11.718020000000001],
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'write0_power': [8.250219],
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'slew_hl': [0.8273725],
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'min_period': 34,
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'delay_hl': [1.085861],
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'slew_lh': [0.5730144]}
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golden_data = {'delay_hl': [11.69536],
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'delay_lh': [1.260921],
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'leakage_power': 0.00039469710000000004,
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'min_period': 20.0,
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'read0_power': [4.40238],
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'read1_power': [4.126633],
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'slew_hl': [1.259555],
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'slew_lh': [0.9150649],
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'write0_power': [4.988347],
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'write1_power': [4.473887]}
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else:
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self.assertTrue(False) # other techs fail
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@ -79,7 +79,7 @@ class openram_test(unittest.TestCase):
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if not data_matches:
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import pprint
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data_string=pprint.pformat(data)
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debug.info(0,"Consider replacing data in unit test with:\n"+data_string)
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debug.info(0,"Data exceeded {:.1f}% tolerance:\n".format(error_tolerance*100)+data_string)
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return data_matches
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