mirror of https://github.com/VLSIDA/OpenRAM.git
Refactor banked SRAM into multiple files and dynamically load in SRAM
This commit is contained in:
Matt Guthaus
parent
19c53cd50c
commit
d95a1925d4
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@ -1,4 +1,4 @@
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import hierarchy_design
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from hierarchy_design import hierarchy_design
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import contact
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import globals
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import verify
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@ -7,7 +7,7 @@ import os
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from globals import OPTS
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class design(hierarchy_design.hierarchy_design):
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class design(hierarchy_design):
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"""
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This is the same as the hierarchy_design class except it contains
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some DRC constants and analytical models for other modules to reuse.
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@ -15,7 +15,7 @@ class design(hierarchy_design.hierarchy_design):
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"""
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def __init__(self, name):
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hierarchy_design.hierarchy_design.__init__(self,name)
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hierarchy_design.__init__(self,name)
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self.setup_drc_constants()
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620
compiler/sram.py
620
compiler/sram.py
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@ -1,19 +1,17 @@
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import sys
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from tech import drc, spice
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import debug
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import design
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from math import log,sqrt,ceil
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import contact
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from bank import bank
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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import datetime
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import getpass
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import debug
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import design
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from sram_1bank import sram_1bank
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from sram_2bank import sram_2bank
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from sram_4bank import sram_4bank
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from math import log,sqrt,ceil
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from vector import vector
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from globals import OPTS, print_time
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class sram(design.design):
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class sram(sram_1bank,sram_2bank,sram_4bank):
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"""
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Dynamically generated SRAM by connecting banks to control logic. The
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number of banks should be 1 , 2 or 4
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@ -35,8 +33,8 @@ class sram(design.design):
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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import design
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design.design.name_map=[]
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from design import design
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design.name_map=[]
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self.word_size = word_size
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self.num_words = num_words
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@ -46,12 +44,20 @@ class sram(design.design):
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self.num_words))
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start_time = datetime.datetime.now()
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design.design.__init__(self, name)
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self.compute_sizes()
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if self.num_banks == 1:
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sram_1bank.__init__(self,name)
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elif self.num_banks == 2:
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sram_2bank.__init__(self,name)
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elif self.num_banks == 4:
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sram_4bank.__init__(self,name)
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else:
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debug.error("Invalid number of banks.",-1)
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self.control_size = 6
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self.bank_to_bus_distance = 5*self.m3_width
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self.compute_sizes()
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self.create_modules()
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self.add_pins()
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self.create_layout()
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@ -151,157 +157,11 @@ class sram(design.design):
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def create_layout(self):
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""" Layout creation """
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if self.num_banks == 1:
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sram_1bank.sram_1bank.__init__()
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elif self.num_banks == 2:
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self.add_two_bank_modules()
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self.route_two_banks()
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elif self.num_banks == 4:
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self.add_four_bank_modules()
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self.route_four_banks()
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else:
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debug.error("Invalid number of banks.",-1)
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def add_four_bank_modules(self):
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""" Adds the modules and the buses to the top level """
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self.compute_bus_sizes()
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self.add_four_banks()
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self.compute_four_bank_offsets()
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self.add_busses()
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self.add_four_bank_logic()
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self.width = self.bank_inst[1].ur().x
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self.height = max(self.control_logic_inst.uy(),self.msb_decoder_inst.uy())
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def add_two_bank_modules(self):
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""" Adds the modules and the buses to the top level """
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self.compute_bus_sizes()
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self.add_two_banks()
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self.compute_two_bank_offsets()
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self.add_busses()
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self.add_two_bank_logic()
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self.width = self.bank_inst[1].ur().x
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self.height = self.control_logic_inst.uy()
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def add_single_bank_modules(self):
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"""
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This adds the moduels for a single bank SRAM with control
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logic.
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"""
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# No orientation or offset
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self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
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# 3/5/18 MRG: Cannot reference positions inside submodules because boundaries
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# are not recomputed using instance placement. So, place the control logic such that it aligns
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# with the top of the SRAM.
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control_pos = vector(-self.control_logic.width - self.m3_pitch,
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3*self.supply_rail_width)
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self.add_control_logic(position=control_pos)
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# Leave room for the control routes to the left of the flops
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addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
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control_pos.y + self.control_logic.height + self.m1_pitch)
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self.add_addr_dff(addr_pos)
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# two supply rails are already included in the bank, so just 2 here.
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self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
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self.height = self.bank.height
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def route_shared_banks(self):
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""" Route the shared signals for two and four bank configurations. """
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# create the input control pins
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for n in self.control_logic_inputs + ["clk"]:
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self.copy_layout_pin(self.control_logic_inst, n)
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# connect the control logic to the control bus
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for n in self.control_logic_outputs + ["vdd", "gnd"]:
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pins = self.control_logic_inst.get_pins(n)
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for pin in pins:
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if pin.layer=="metal2":
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pin_pos = pin.bc()
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break
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rail_pos = vector(pin_pos.x,self.horz_control_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal1","via1","metal2"),rail_pos)
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# connect the control logic cross bar
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for n in self.control_logic_outputs:
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cross_pos = vector(self.vert_control_bus_positions[n].x,self.horz_control_bus_positions[n].y)
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self.add_via_center(("metal1","via1","metal2"),cross_pos)
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# connect the bank select signals to the vertical bus
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for i in range(self.num_banks):
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pin = self.bank_inst[i].get_pin("bank_sel")
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pin_pos = pin.rc() if i==0 else pin.lc()
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rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,pin_pos.y)
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self.add_path("metal3",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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def route_four_banks(self):
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""" Route all of the signals for the four bank SRAM. """
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self.route_shared_banks()
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# connect the data output to the data bus
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for n in self.data_bus_names:
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for i in [0,1]:
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pin_pos = self.bank_inst[i].get_pin(n).bc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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for i in [2,3]:
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pin_pos = self.bank_inst[i].get_pin(n).uc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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# route msb address bits
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# route 2:4 decoder
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self.route_double_msb_address()
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# connect the banks to the vertical address bus
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# connect the banks to the vertical control bus
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for n in self.addr_bus_names + self.control_bus_names:
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# Skip these from the horizontal bus
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if n in ["vdd", "gnd"]: continue
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# This will be the bank select, so skip it
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if n in self.msb_bank_sel_addr: continue
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for bank_id in [0,2]:
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pin0_pos = self.bank_inst[bank_id].get_pin(n).rc()
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pin1_pos = self.bank_inst[bank_id+1].get_pin(n).lc()
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rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
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self.add_path("metal3",[pin0_pos,pin1_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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self.route_bank_supply_rails(left_banks=[0,2], bottom_banks=[2,3])
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""" Layout creation """
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self.add_modules()
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self.route()
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def compute_bus_sizes(self):
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""" Compute the independent bus widths shared between two and four bank SRAMs """
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@ -328,63 +188,6 @@ class sram(design.design):
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"Bank is too small compared to control logic.")
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def compute_four_bank_offsets(self):
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""" Compute the overall offsets for a four bank SRAM """
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# The main difference is that the four bank SRAM has the data bus in the middle of the four banks
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# as opposed to the top of the banks.
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# In 4 bank SRAM, the height is determined by the bank decoder and address flop
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self.vertical_bus_height = 2*self.bank.height + 4*self.bank_to_bus_distance + self.data_bus_height \
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+ self.supply_bus_height + self.msb_decoder.height + self.msb_address.width
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# The address bus extends down through the power rails, but control and bank_sel bus don't
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self.addr_bus_height = self.vertical_bus_height
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self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
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self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
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self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height \
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+ self.bank.height + 2*self.bank_to_bus_distance)
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self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
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self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
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self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
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# Control is placed at the top above the control bus and everything
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self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
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# Bank select flops get put to the right of control logic above bank1 and the buses
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# Leave a pitch to get the vdd rails up to M2
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self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
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self.supply_bus_offset.y + self.supply_bus_height \
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+ 2*self.m1_pitch + self.msb_address.width)
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# Decoder goes above the MSB address flops, and is flipped in Y
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# separate the two by a bank to bus distance for nwell rules, just in case
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self.msb_decoder_position = self.msb_address_position + vector(self.msb_decoder.width, self.bank_to_bus_distance)
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def compute_two_bank_offsets(self):
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""" Compute the overall offsets for a two bank SRAM """
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# In 2 bank SRAM, the height is determined by the control bus which is higher than the msb address
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self.vertical_bus_height = self.bank.height + 2*self.bank_to_bus_distance + self.data_bus_height + self.control_bus_height
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# The address bus extends down through the power rails, but control and bank_sel bus don't
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self.addr_bus_height = self.vertical_bus_height
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self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
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self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
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self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height)
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self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
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self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
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self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
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# Control is placed at the top above the control bus and everything
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self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
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# Bank select flops get put to the right of control logic above bank1 and the buses
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# Leave a pitch to get the vdd rails up to M2
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self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
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self.supply_bus_offset.y + self.supply_bus_height \
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+ 2*self.m1_pitch + self.msb_address.width)
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def add_busses(self):
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""" Add the horizontal and vertical busses """
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@ -443,293 +246,8 @@ class sram(design.design):
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length=self.control_bus_width))
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def add_two_bank_logic(self):
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""" Add the control and MSB logic """
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self.add_control_logic(position=self.control_logic_position)
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self.msb_address_inst = self.add_inst(name="msb_address",
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mod=self.msb_address,
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offset=self.msb_address_position,
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rotate=270)
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self.msb_bank_sel_addr = "ADDR[{}]".format(self.addr_size-1)
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self.connect_inst([self.msb_bank_sel_addr,"bank_sel[1]","bank_sel[0]","clk_buf", "vdd", "gnd"])
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def add_four_bank_logic(self):
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""" Add the control and MSB decode/bank select logic for four banks """
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self.add_control_logic(position=self.control_logic_position)
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self.msb_address_inst = self.add_inst(name="msb_address",
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mod=self.msb_address,
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offset=self.msb_address_position,
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rotate=270)
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self.msb_bank_sel_addr = ["ADDR[{}]".format(i) for i in range(self.addr_size-2,self.addr_size,1)]
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temp = list(self.msb_bank_sel_addr)
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temp.extend(["msb{0}[{1}]".format(j,i) for i in range(2) for j in ["","_bar"]])
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temp.extend(["clk_buf", "vdd", "gnd"])
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self.connect_inst(temp)
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self.msb_decoder_inst = self.add_inst(name="msb_decoder",
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mod=self.msb_decoder,
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offset=self.msb_decoder_position,
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mirror="MY")
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temp = ["msb[{}]".format(i) for i in range(2)]
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temp.extend(["bank_sel[{}]".format(i) for i in range(4)])
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def route_two_banks(self):
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""" Route all of the signals for the two bank SRAM. """
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self.route_shared_banks()
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# connect the horizontal control bus to the vertical bus
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# connect the data output to the data bus
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for n in self.data_bus_names:
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for i in [0,1]:
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pin_pos = self.bank_inst[i].get_pin(n).uc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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self.route_single_msb_address()
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# connect the banks to the vertical address bus
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# connect the banks to the vertical control bus
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for n in self.addr_bus_names + self.control_bus_names:
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# Skip these from the horizontal bus
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if n in ["vdd", "gnd"]: continue
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# This will be the bank select, so skip it
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if n == self.msb_bank_sel_addr: continue
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pin0_pos = self.bank_inst[0].get_pin(n).rc()
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pin1_pos = self.bank_inst[1].get_pin(n).lc()
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rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
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self.add_path("metal3",[pin0_pos,pin1_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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def route_double_msb_address(self):
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""" Route two MSB address bits and the bank decoder for 4-bank SRAM """
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# connect the MSB flops to the address input bus
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for i in [0,1]:
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msb_pins = self.msb_address_inst.get_pins("din[{}]".format(i))
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for msb_pin in msb_pins:
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if msb_pin.layer == "metal3":
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msb_pin_pos = msb_pin.lc()
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break
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rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr[i]].x,msb_pin_pos.y)
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self.add_path("metal3",[msb_pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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# Connect clk
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clk_pin = self.msb_address_inst.get_pin("clk")
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clk_pos = clk_pin.bc()
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rail_pos = self.horz_control_bus_positions["clk_buf"]
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bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
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self.add_path("metal1",[clk_pos,bend_pos,rail_pos])
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# Connect bank decoder outputs to the bank select vertical bus wires
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for i in range(self.num_banks):
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msb_pin = self.msb_decoder_inst.get_pin("out[{}]".format(i))
|
||||
msb_pin_pos = msb_pin.lc()
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,msb_pin_pos.y)
|
||||
self.add_path("metal1",[msb_pin_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
# connect MSB flop outputs to the bank decoder inputs
|
||||
msb_pin = self.msb_address_inst.get_pin("dout[0]")
|
||||
msb_pin_pos = msb_pin.rc()
|
||||
in_pin = self.msb_decoder_inst.get_pin("in[0]")
|
||||
in_pos = in_pin.bc() + vector(0,1*self.m2_pitch,) # pin is up from bottom
|
||||
out_pos = msb_pin_pos + vector(1*self.m2_pitch,0) # route out to the right
|
||||
up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
|
||||
self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),in_pos)
|
||||
self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
|
||||
|
||||
msb_pin = self.msb_address_inst.get_pin("dout[1]")
|
||||
msb_pin_pos = msb_pin.rc()
|
||||
in_pin = self.msb_decoder_inst.get_pin("in[1]")
|
||||
in_pos = in_pin.bc() + vector(0,self.bitcell.height+self.m2_pitch) # route the next row up
|
||||
out_pos = msb_pin_pos + vector(2*self.m2_pitch,0) # route out to the right
|
||||
up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
|
||||
self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),in_pos)
|
||||
self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
|
||||
|
||||
self.route_double_msb_address_supplies()
|
||||
|
||||
def route_double_msb_address_supplies(self):
|
||||
""" Route the vdd/gnd bits of the 2-bit bank decoder. """
|
||||
|
||||
# Route the right-most vdd/gnd of the right upper bank to the top of the decoder
|
||||
vdd_pins = self.bank_inst[1].get_pins("vdd")
|
||||
left_bank_vdd_pin = None
|
||||
right_bank_vdd_pin = None
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal2":
|
||||
continue
|
||||
if left_bank_vdd_pin == None or vdd_pin.lx()<left_bank_vdd_pin.lx():
|
||||
left_bank_vdd_pin = vdd_pin
|
||||
if right_bank_vdd_pin == None or vdd_pin.lx()>right_bank_vdd_pin.lx():
|
||||
right_bank_vdd_pin = vdd_pin
|
||||
# Route to top
|
||||
self.add_rect(layer="metal2",
|
||||
offset=vdd_pin.ul(),
|
||||
height=self.height-vdd_pin.uy(),
|
||||
width=vdd_pin.width())
|
||||
|
||||
gnd_pins = self.bank_inst[1].get_pins("gnd")
|
||||
left_bank_gnd_pin = None
|
||||
right_bank_gnd_pin = None
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2":
|
||||
continue
|
||||
if left_bank_gnd_pin == None or gnd_pin.lx()<left_bank_gnd_pin.lx():
|
||||
left_bank_gnd_pin = gnd_pin
|
||||
if right_bank_gnd_pin == None or gnd_pin.lx()>right_bank_gnd_pin.lx():
|
||||
right_bank_gnd_pin = gnd_pin
|
||||
# Route to top
|
||||
self.add_rect(layer="metal2",
|
||||
offset=gnd_pin.ul(),
|
||||
height=self.height-gnd_pin.uy(),
|
||||
width=gnd_pin.width())
|
||||
|
||||
# Connect bank decoder vdd/gnd supplies using the previous bank pins
|
||||
vdd_pins = self.msb_decoder_inst.get_pins("vdd")
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_vdd_pin.cx(),vdd_pin.cy())
|
||||
rail2_pos = vector(right_bank_vdd_pin.cx(),vdd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,rail2_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail2_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
gnd_pins = self.msb_decoder_inst.get_pins("gnd")
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal1":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
rail2_pos = vector(right_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,rail2_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail2_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
|
||||
# connect the bank MSB flop supplies
|
||||
vdd_pins = self.msb_address_inst.get_pins("vdd")
|
||||
# vdd pins go down to the rail
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1":
|
||||
continue
|
||||
vdd_pos = vdd_pin.bc()
|
||||
down_pos = vdd_pos - vector(0,self.m1_pitch)
|
||||
rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
|
||||
self.add_path("metal1",[vdd_pos,down_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=down_pos,
|
||||
rotate=90)
|
||||
self.add_path("metal2",[down_pos,rail_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail_pos)
|
||||
# gnd pins go right to the rail
|
||||
gnd_pins = self.msb_address_inst.get_pins("gnd")
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,gnd_pin.lc()])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=gnd_pin.lc(),
|
||||
rotate=90)
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
|
||||
def route_single_msb_address(self):
|
||||
""" Route one MSB address bit for 2-bank SRAM """
|
||||
|
||||
# connect the bank MSB flop supplies
|
||||
vdd_pins = self.msb_address_inst.get_pins("vdd")
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1": continue
|
||||
vdd_pos = vdd_pin.bc()
|
||||
down_pos = vdd_pos - vector(0,self.m1_pitch)
|
||||
rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
|
||||
self.add_path("metal1",[vdd_pos,down_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),down_pos,rotate=90)
|
||||
self.add_path("metal2",[down_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
gnd_pins = self.msb_address_inst.get_pins("gnd")
|
||||
# Only add the ground connection to the lowest metal2 rail in the flop array
|
||||
# FIXME: SCMOS doesn't have a vertical rail in the cell, or we could use those
|
||||
lowest_y = None
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2": continue
|
||||
if lowest_y==None or gnd_pin.by()<lowest_y:
|
||||
lowest_y=gnd_pin.by()
|
||||
gnd_pos = gnd_pin.ur()
|
||||
rail_pos = vector(gnd_pos.x,self.horz_control_bus_positions["gnd"].y)
|
||||
self.add_path("metal2",[gnd_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
# connect the MSB flop to the address input bus
|
||||
msb_pins = self.msb_address_inst.get_pins("din[0]")
|
||||
for msb_pin in msb_pins:
|
||||
if msb_pin.layer == "metal3":
|
||||
msb_pin_pos = msb_pin.lc()
|
||||
break
|
||||
rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr].x,msb_pin_pos.y)
|
||||
self.add_path("metal3",[msb_pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect the output bar to select 0
|
||||
msb_out_pin = self.msb_address_inst.get_pin("dout_bar[0]")
|
||||
msb_out_pos = msb_out_pin.rc()
|
||||
out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
|
||||
out_extend_up_pos = out_extend_right_pos + vector(0,self.m2_width)
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[0]"].x,out_extend_up_pos.y)
|
||||
self.add_path("metal2",[msb_out_pos,out_extend_right_pos,out_extend_up_pos])
|
||||
self.add_wire(("metal3","via2","metal2"),[out_extend_right_pos,out_extend_up_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect the output to select 1
|
||||
msb_out_pin = self.msb_address_inst.get_pin("dout[0]")
|
||||
msb_out_pos = msb_out_pin.rc()
|
||||
out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
|
||||
out_extend_down_pos = out_extend_right_pos - vector(0,2*self.m1_pitch)
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[1]"].x,out_extend_down_pos.y)
|
||||
self.add_path("metal2",[msb_out_pos,out_extend_right_pos,out_extend_down_pos])
|
||||
self.add_wire(("metal3","via2","metal2"),[out_extend_right_pos,out_extend_down_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect clk
|
||||
clk_pin = self.msb_address_inst.get_pin("clk")
|
||||
clk_pos = clk_pin.bc()
|
||||
rail_pos = self.horz_control_bus_positions["clk_buf"]
|
||||
bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
|
||||
self.add_path("metal1",[clk_pos,bend_pos,rail_pos])
|
||||
|
||||
|
||||
|
||||
def route_vdd_gnd(self):
|
||||
""" Propagate all vdd/gnd pins up to this level for all modules """
|
||||
|
|
@ -762,7 +280,7 @@ class sram(design.design):
|
|||
|
||||
def create_multi_bank_modules(self):
|
||||
""" Create the multibank address flops and bank decoder """
|
||||
|
||||
from dff_buf_array import dff_buf_array
|
||||
self.msb_address = dff_buf_array(name="msb_address",
|
||||
rows=1,
|
||||
columns=self.num_banks/2)
|
||||
|
|
@ -775,16 +293,19 @@ class sram(design.design):
|
|||
def create_modules(self):
|
||||
""" Create all the modules that will be used """
|
||||
|
||||
from control_logic import control_logic
|
||||
# Create the control logic module
|
||||
self.control_logic = self.mod_control_logic(num_rows=self.num_rows)
|
||||
self.add_mod(self.control_logic)
|
||||
|
||||
# Create the address and control flops (but not the clk)
|
||||
dff_size = self.addr_size
|
||||
from dff_array import dff_array
|
||||
self.addr_dff = dff_array(name="dff_array", rows=dff_size, columns=1)
|
||||
self.add_mod(self.addr_dff)
|
||||
|
||||
# Create the bank module (up to four are instantiated)
|
||||
from bank import bank
|
||||
self.bank = bank(word_size=self.word_size,
|
||||
num_words=self.num_words_per_bank,
|
||||
words_per_row=self.words_per_row,
|
||||
|
|
@ -895,51 +416,9 @@ class sram(design.design):
|
|||
layer="metal2",
|
||||
offset=self.vert_control_bus_positions[n])
|
||||
|
||||
def add_single_bank_pins(self):
|
||||
"""
|
||||
Add the top-level pins for a single bank SRAM with control.
|
||||
"""
|
||||
|
||||
for i in range(self.word_size):
|
||||
self.copy_layout_pin(self.bank_inst, "DOUT[{}]".format(i))
|
||||
|
||||
for i in range(self.addr_size):
|
||||
self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
|
||||
|
||||
|
||||
def add_two_banks(self):
|
||||
# Placement of bank 0 (left)
|
||||
bank_position_0 = vector(self.bank.width,
|
||||
self.bank.height)
|
||||
self.bank_inst=[self.add_bank(0, bank_position_0, -1, -1)]
|
||||
|
||||
# Placement of bank 1 (right)
|
||||
x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
|
||||
bank_position_1 = vector(x_off, bank_position_0.y)
|
||||
self.bank_inst.append(self.add_bank(1, bank_position_1, -1, 1))
|
||||
|
||||
|
||||
def add_four_banks(self):
|
||||
|
||||
# Placement of bank 0 (upper left)
|
||||
bank_position_0 = vector(self.bank.width,
|
||||
self.bank.height + self.data_bus_height + 2*self.bank_to_bus_distance)
|
||||
self.bank_inst=[self.add_bank(0, bank_position_0, 1, -1)]
|
||||
|
||||
# Placement of bank 1 (upper right)
|
||||
x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
|
||||
bank_position_1 = vector(x_off, bank_position_0.y)
|
||||
self.bank_inst.append(self.add_bank(1, bank_position_1, 1, 1))
|
||||
|
||||
# Placement of bank 2 (bottom left)
|
||||
y_off = self.bank.height
|
||||
bank_position_2 = vector(bank_position_0.x, y_off)
|
||||
self.bank_inst.append(self.add_bank(2, bank_position_2, -1, -1))
|
||||
|
||||
# Placement of bank 3 (bottom right)
|
||||
bank_position_3 = vector(bank_position_1.x, bank_position_2.y)
|
||||
self.bank_inst.append(self.add_bank(3, bank_position_3, -1, 1))
|
||||
|
||||
|
||||
def connect_rail_from_left_m2m3(self, src_pin, dest_pin):
|
||||
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
|
||||
|
|
@ -956,49 +435,6 @@ class sram(design.design):
|
|||
out_pos = vector(dest_pin.cx(), in_pos.y)
|
||||
self.add_wire(("metal2","via1","metal1"),[in_pos, out_pos, out_pos - vector(0,self.m2_pitch)])
|
||||
|
||||
def route_single_bank(self):
|
||||
""" Route a single bank SRAM """
|
||||
|
||||
# Route the outputs from the control logic module
|
||||
for n in self.control_logic_outputs:
|
||||
src_pin = self.control_logic_inst.get_pin(n)
|
||||
dest_pin = self.bank_inst.get_pin(n)
|
||||
self.connect_rail_from_left_m2m3(src_pin, dest_pin)
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=src_pin.rc(),
|
||||
rotate=90)
|
||||
|
||||
|
||||
# Connect the output of the flops to the bank pins
|
||||
for i in range(self.addr_size):
|
||||
flop_name = "dout[{}]".format(i)
|
||||
bank_name = "A[{}]".format(i)
|
||||
flop_pin = self.addr_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = vector(bank_pin.cx(),flop_pos.y)
|
||||
self.add_path("metal3",[flop_pos, bank_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
rotate=90)
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=bank_pos,
|
||||
rotate=90)
|
||||
|
||||
# Connect the control pins as inputs
|
||||
for n in self.control_logic_inputs + ["clk"]:
|
||||
self.copy_layout_pin(self.control_logic_inst, n)
|
||||
|
||||
# Connect the clock between the flops and control module
|
||||
flop_pin = self.addr_dff_inst.get_pin("clk")
|
||||
ctrl_pin = self.control_logic_inst.get_pin("clk_buf")
|
||||
flop_pos = flop_pin.uc()
|
||||
ctrl_pos = ctrl_pin.bc()
|
||||
mid_ypos = 0.5*(ctrl_pos.y+flop_pos.y)
|
||||
mid1_pos = vector(flop_pos.x, mid_ypos)
|
||||
mid2_pos = vector(ctrl_pos.x, mid_ypos)
|
||||
self.add_wire(("metal1","via1","metal2"),[flop_pin.uc(), mid1_pos, mid2_pos, ctrl_pin.bc()])
|
||||
|
||||
|
||||
|
||||
def sp_write(self, sp_name):
|
||||
|
|
|
|||
|
|
@ -0,0 +1,101 @@
|
|||
import sys
|
||||
from tech import drc, spice
|
||||
import debug
|
||||
from math import log,sqrt,ceil
|
||||
import datetime
|
||||
import getpass
|
||||
from vector import vector
|
||||
from globals import OPTS, print_time
|
||||
|
||||
from design import design
|
||||
from bank import bank
|
||||
from dff_buf_array import dff_buf_array
|
||||
from dff_array import dff_array
|
||||
|
||||
|
||||
class sram_1bank(design):
|
||||
"""
|
||||
Procedures specific to a two bank SRAM.
|
||||
"""
|
||||
def __init__(self, name):
|
||||
design.__init__(self, name)
|
||||
|
||||
def add_modules(self):
|
||||
"""
|
||||
This adds the moduels for a single bank SRAM with control
|
||||
logic.
|
||||
"""
|
||||
|
||||
# No orientation or offset
|
||||
self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
|
||||
|
||||
# 3/5/18 MRG: Cannot reference positions inside submodules because boundaries
|
||||
# are not recomputed using instance placement. So, place the control logic such that it aligns
|
||||
# with the top of the SRAM.
|
||||
control_pos = vector(-self.control_logic.width - self.m3_pitch,
|
||||
3*self.supply_rail_width)
|
||||
self.add_control_logic(position=control_pos)
|
||||
|
||||
# Leave room for the control routes to the left of the flops
|
||||
addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
|
||||
control_pos.y + self.control_logic.height + self.m1_pitch)
|
||||
self.add_addr_dff(addr_pos)
|
||||
|
||||
# two supply rails are already included in the bank, so just 2 here.
|
||||
self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
|
||||
self.height = self.bank.height
|
||||
|
||||
def add_pins(self):
|
||||
"""
|
||||
Add the top-level pins for a single bank SRAM with control.
|
||||
"""
|
||||
|
||||
for i in range(self.word_size):
|
||||
self.copy_layout_pin(self.bank_inst, "DOUT[{}]".format(i))
|
||||
|
||||
for i in range(self.addr_size):
|
||||
self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
|
||||
|
||||
def route(self):
|
||||
""" Route a single bank SRAM """
|
||||
|
||||
# Route the outputs from the control logic module
|
||||
for n in self.control_logic_outputs:
|
||||
src_pin = self.control_logic_inst.get_pin(n)
|
||||
dest_pin = self.bank_inst.get_pin(n)
|
||||
self.connect_rail_from_left_m2m3(src_pin, dest_pin)
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=src_pin.rc(),
|
||||
rotate=90)
|
||||
|
||||
|
||||
# Connect the output of the flops to the bank pins
|
||||
for i in range(self.addr_size):
|
||||
flop_name = "dout[{}]".format(i)
|
||||
bank_name = "A[{}]".format(i)
|
||||
flop_pin = self.addr_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = vector(bank_pin.cx(),flop_pos.y)
|
||||
self.add_path("metal3",[flop_pos, bank_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
rotate=90)
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=bank_pos,
|
||||
rotate=90)
|
||||
|
||||
# Connect the control pins as inputs
|
||||
for n in self.control_logic_inputs + ["clk"]:
|
||||
self.copy_layout_pin(self.control_logic_inst, n)
|
||||
|
||||
# Connect the clock between the flops and control module
|
||||
flop_pin = self.addr_dff_inst.get_pin("clk")
|
||||
ctrl_pin = self.control_logic_inst.get_pin("clk_buf")
|
||||
flop_pos = flop_pin.uc()
|
||||
ctrl_pos = ctrl_pin.bc()
|
||||
mid_ypos = 0.5*(ctrl_pos.y+flop_pos.y)
|
||||
mid1_pos = vector(flop_pos.x, mid_ypos)
|
||||
mid2_pos = vector(ctrl_pos.x, mid_ypos)
|
||||
self.add_wire(("metal1","via1","metal2"),[flop_pin.uc(), mid1_pos, mid2_pos, ctrl_pin.bc()])
|
||||
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
import sys
|
||||
from tech import drc, spice
|
||||
import debug
|
||||
import design
|
||||
from math import log,sqrt,ceil
|
||||
import contact
|
||||
from bank import bank
|
||||
from dff_buf_array import dff_buf_array
|
||||
from dff_array import dff_array
|
||||
import datetime
|
||||
import getpass
|
||||
from vector import vector
|
||||
from globals import OPTS, print_time
|
||||
|
||||
class sram_2bank(design.design):
|
||||
"""
|
||||
Procedures specific to a two bank SRAM.
|
||||
"""
|
||||
def __init__(self, name):
|
||||
design.__init__(self, name)
|
||||
|
||||
def compute_bank_offsets(self):
|
||||
""" Compute the overall offsets for a two bank SRAM """
|
||||
|
||||
# In 2 bank SRAM, the height is determined by the control bus which is higher than the msb address
|
||||
self.vertical_bus_height = self.bank.height + 2*self.bank_to_bus_distance + self.data_bus_height + self.control_bus_height
|
||||
# The address bus extends down through the power rails, but control and bank_sel bus don't
|
||||
self.addr_bus_height = self.vertical_bus_height
|
||||
|
||||
self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
|
||||
self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
|
||||
self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height)
|
||||
self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
|
||||
self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
|
||||
self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
|
||||
|
||||
# Control is placed at the top above the control bus and everything
|
||||
self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
|
||||
|
||||
# Bank select flops get put to the right of control logic above bank1 and the buses
|
||||
# Leave a pitch to get the vdd rails up to M2
|
||||
self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
|
||||
self.supply_bus_offset.y + self.supply_bus_height \
|
||||
+ 2*self.m1_pitch + self.msb_address.width)
|
||||
|
||||
def add_modules(self):
|
||||
""" Adds the modules and the buses to the top level """
|
||||
|
||||
self.compute_bus_sizes()
|
||||
|
||||
self.add_banks()
|
||||
|
||||
self.compute_bank_offsets()
|
||||
|
||||
self.add_busses()
|
||||
|
||||
self.add_logic()
|
||||
|
||||
self.width = self.bank_inst[1].ur().x
|
||||
self.height = self.control_logic_inst.uy()
|
||||
|
||||
|
||||
|
||||
def add_banks(self):
|
||||
# Placement of bank 0 (left)
|
||||
bank_position_0 = vector(self.bank.width,
|
||||
self.bank.height)
|
||||
self.bank_inst=[self.add_bank(0, bank_position_0, -1, -1)]
|
||||
|
||||
# Placement of bank 1 (right)
|
||||
x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
|
||||
bank_position_1 = vector(x_off, bank_position_0.y)
|
||||
self.bank_inst.append(self.add_bank(1, bank_position_1, -1, 1))
|
||||
|
||||
def add_logic(self):
|
||||
""" Add the control and MSB logic """
|
||||
|
||||
self.add_control_logic(position=self.control_logic_position)
|
||||
|
||||
self.msb_address_inst = self.add_inst(name="msb_address",
|
||||
mod=self.msb_address,
|
||||
offset=self.msb_address_position,
|
||||
rotate=270)
|
||||
self.msb_bank_sel_addr = "ADDR[{}]".format(self.addr_size-1)
|
||||
self.connect_inst([self.msb_bank_sel_addr,"bank_sel[1]","bank_sel[0]","clk_buf", "vdd", "gnd"])
|
||||
|
||||
|
||||
def route_shared_banks(self):
|
||||
""" Route the shared signals for two and four bank configurations. """
|
||||
|
||||
# create the input control pins
|
||||
for n in self.control_logic_inputs + ["clk"]:
|
||||
self.copy_layout_pin(self.control_logic_inst, n)
|
||||
|
||||
# connect the control logic to the control bus
|
||||
for n in self.control_logic_outputs + ["vdd", "gnd"]:
|
||||
pins = self.control_logic_inst.get_pins(n)
|
||||
for pin in pins:
|
||||
if pin.layer=="metal2":
|
||||
pin_pos = pin.bc()
|
||||
break
|
||||
rail_pos = vector(pin_pos.x,self.horz_control_bus_positions[n].y)
|
||||
self.add_path("metal2",[pin_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
# connect the control logic cross bar
|
||||
for n in self.control_logic_outputs:
|
||||
cross_pos = vector(self.vert_control_bus_positions[n].x,self.horz_control_bus_positions[n].y)
|
||||
self.add_via_center(("metal1","via1","metal2"),cross_pos)
|
||||
|
||||
# connect the bank select signals to the vertical bus
|
||||
for i in range(self.num_banks):
|
||||
pin = self.bank_inst[i].get_pin("bank_sel")
|
||||
pin_pos = pin.rc() if i==0 else pin.lc()
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,pin_pos.y)
|
||||
self.add_path("metal3",[pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
def route_single_msb_address(self):
|
||||
""" Route one MSB address bit for 2-bank SRAM """
|
||||
|
||||
# connect the bank MSB flop supplies
|
||||
vdd_pins = self.msb_address_inst.get_pins("vdd")
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1": continue
|
||||
vdd_pos = vdd_pin.bc()
|
||||
down_pos = vdd_pos - vector(0,self.m1_pitch)
|
||||
rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
|
||||
self.add_path("metal1",[vdd_pos,down_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),down_pos,rotate=90)
|
||||
self.add_path("metal2",[down_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
gnd_pins = self.msb_address_inst.get_pins("gnd")
|
||||
# Only add the ground connection to the lowest metal2 rail in the flop array
|
||||
# FIXME: SCMOS doesn't have a vertical rail in the cell, or we could use those
|
||||
lowest_y = None
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2": continue
|
||||
if lowest_y==None or gnd_pin.by()<lowest_y:
|
||||
lowest_y=gnd_pin.by()
|
||||
gnd_pos = gnd_pin.ur()
|
||||
rail_pos = vector(gnd_pos.x,self.horz_control_bus_positions["gnd"].y)
|
||||
self.add_path("metal2",[gnd_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
# connect the MSB flop to the address input bus
|
||||
msb_pins = self.msb_address_inst.get_pins("din[0]")
|
||||
for msb_pin in msb_pins:
|
||||
if msb_pin.layer == "metal3":
|
||||
msb_pin_pos = msb_pin.lc()
|
||||
break
|
||||
rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr].x,msb_pin_pos.y)
|
||||
self.add_path("metal3",[msb_pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect the output bar to select 0
|
||||
msb_out_pin = self.msb_address_inst.get_pin("dout_bar[0]")
|
||||
msb_out_pos = msb_out_pin.rc()
|
||||
out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
|
||||
out_extend_up_pos = out_extend_right_pos + vector(0,self.m2_width)
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[0]"].x,out_extend_up_pos.y)
|
||||
self.add_path("metal2",[msb_out_pos,out_extend_right_pos,out_extend_up_pos])
|
||||
self.add_wire(("metal3","via2","metal2"),[out_extend_right_pos,out_extend_up_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect the output to select 1
|
||||
msb_out_pin = self.msb_address_inst.get_pin("dout[0]")
|
||||
msb_out_pos = msb_out_pin.rc()
|
||||
out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
|
||||
out_extend_down_pos = out_extend_right_pos - vector(0,2*self.m1_pitch)
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[1]"].x,out_extend_down_pos.y)
|
||||
self.add_path("metal2",[msb_out_pos,out_extend_right_pos,out_extend_down_pos])
|
||||
self.add_wire(("metal3","via2","metal2"),[out_extend_right_pos,out_extend_down_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect clk
|
||||
clk_pin = self.msb_address_inst.get_pin("clk")
|
||||
clk_pos = clk_pin.bc()
|
||||
rail_pos = self.horz_control_bus_positions["clk_buf"]
|
||||
bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
|
||||
self.add_path("metal1",[clk_pos,bend_pos,rail_pos])
|
||||
|
||||
|
||||
|
||||
def route(self):
|
||||
""" Route all of the signals for the two bank SRAM. """
|
||||
|
||||
self.route_shared_banks()
|
||||
|
||||
# connect the horizontal control bus to the vertical bus
|
||||
# connect the data output to the data bus
|
||||
for n in self.data_bus_names:
|
||||
for i in [0,1]:
|
||||
pin_pos = self.bank_inst[i].get_pin(n).uc()
|
||||
rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
|
||||
self.add_path("metal2",[pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
self.route_single_msb_address()
|
||||
|
||||
# connect the banks to the vertical address bus
|
||||
# connect the banks to the vertical control bus
|
||||
for n in self.addr_bus_names + self.control_bus_names:
|
||||
# Skip these from the horizontal bus
|
||||
if n in ["vdd", "gnd"]: continue
|
||||
# This will be the bank select, so skip it
|
||||
if n == self.msb_bank_sel_addr: continue
|
||||
pin0_pos = self.bank_inst[0].get_pin(n).rc()
|
||||
pin1_pos = self.bank_inst[1].get_pin(n).lc()
|
||||
rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
|
||||
self.add_path("metal3",[pin0_pos,pin1_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
import sys
|
||||
from tech import drc, spice
|
||||
import debug
|
||||
import design
|
||||
from math import log,sqrt,ceil
|
||||
import contact
|
||||
from bank import bank
|
||||
from dff_buf_array import dff_buf_array
|
||||
from dff_array import dff_array
|
||||
import datetime
|
||||
import getpass
|
||||
from vector import vector
|
||||
from globals import OPTS, print_time
|
||||
|
||||
class sram_4bank(design.design):
|
||||
"""
|
||||
Procedures specific to a four bank SRAM.
|
||||
"""
|
||||
def __init__(self, name):
|
||||
design.__init__(self, name)
|
||||
|
||||
def compute_bank_offsets(self):
|
||||
""" Compute the overall offsets for a four bank SRAM """
|
||||
|
||||
# The main difference is that the four bank SRAM has the data bus in the middle of the four banks
|
||||
# as opposed to the top of the banks.
|
||||
|
||||
# In 4 bank SRAM, the height is determined by the bank decoder and address flop
|
||||
self.vertical_bus_height = 2*self.bank.height + 4*self.bank_to_bus_distance + self.data_bus_height \
|
||||
+ self.supply_bus_height + self.msb_decoder.height + self.msb_address.width
|
||||
# The address bus extends down through the power rails, but control and bank_sel bus don't
|
||||
self.addr_bus_height = self.vertical_bus_height
|
||||
|
||||
self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
|
||||
self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
|
||||
self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height \
|
||||
+ self.bank.height + 2*self.bank_to_bus_distance)
|
||||
self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
|
||||
self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
|
||||
self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
|
||||
|
||||
# Control is placed at the top above the control bus and everything
|
||||
self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
|
||||
|
||||
# Bank select flops get put to the right of control logic above bank1 and the buses
|
||||
# Leave a pitch to get the vdd rails up to M2
|
||||
self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
|
||||
self.supply_bus_offset.y + self.supply_bus_height \
|
||||
+ 2*self.m1_pitch + self.msb_address.width)
|
||||
|
||||
# Decoder goes above the MSB address flops, and is flipped in Y
|
||||
# separate the two by a bank to bus distance for nwell rules, just in case
|
||||
self.msb_decoder_position = self.msb_address_position + vector(self.msb_decoder.width, self.bank_to_bus_distance)
|
||||
|
||||
|
||||
def add_modules(self):
|
||||
""" Adds the modules and the buses to the top level """
|
||||
|
||||
self.compute_bus_sizes()
|
||||
|
||||
self.add_banks()
|
||||
|
||||
self.compute_bank_offsets()
|
||||
|
||||
self.add_busses()
|
||||
|
||||
self.add_logic()
|
||||
|
||||
self.width = self.bank_inst[1].ur().x
|
||||
self.height = max(self.control_logic_inst.uy(),self.msb_decoder_inst.uy())
|
||||
|
||||
def add_banks(self):
|
||||
|
||||
# Placement of bank 0 (upper left)
|
||||
bank_position_0 = vector(self.bank.width,
|
||||
self.bank.height + self.data_bus_height + 2*self.bank_to_bus_distance)
|
||||
self.bank_inst=[self.add_bank(0, bank_position_0, 1, -1)]
|
||||
|
||||
# Placement of bank 1 (upper right)
|
||||
x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
|
||||
bank_position_1 = vector(x_off, bank_position_0.y)
|
||||
self.bank_inst.append(self.add_bank(1, bank_position_1, 1, 1))
|
||||
|
||||
# Placement of bank 2 (bottom left)
|
||||
y_off = self.bank.height
|
||||
bank_position_2 = vector(bank_position_0.x, y_off)
|
||||
self.bank_inst.append(self.add_bank(2, bank_position_2, -1, -1))
|
||||
|
||||
# Placement of bank 3 (bottom right)
|
||||
bank_position_3 = vector(bank_position_1.x, bank_position_2.y)
|
||||
self.bank_inst.append(self.add_bank(3, bank_position_3, -1, 1))
|
||||
|
||||
|
||||
|
||||
def add_logic(self):
|
||||
""" Add the control and MSB decode/bank select logic for four banks """
|
||||
|
||||
|
||||
self.add_control_logic(position=self.control_logic_position)
|
||||
|
||||
self.msb_address_inst = self.add_inst(name="msb_address",
|
||||
mod=self.msb_address,
|
||||
offset=self.msb_address_position,
|
||||
rotate=270)
|
||||
|
||||
self.msb_bank_sel_addr = ["ADDR[{}]".format(i) for i in range(self.addr_size-2,self.addr_size,1)]
|
||||
temp = list(self.msb_bank_sel_addr)
|
||||
temp.extend(["msb{0}[{1}]".format(j,i) for i in range(2) for j in ["","_bar"]])
|
||||
temp.extend(["clk_buf", "vdd", "gnd"])
|
||||
self.connect_inst(temp)
|
||||
|
||||
self.msb_decoder_inst = self.add_inst(name="msb_decoder",
|
||||
mod=self.msb_decoder,
|
||||
offset=self.msb_decoder_position,
|
||||
mirror="MY")
|
||||
temp = ["msb[{}]".format(i) for i in range(2)]
|
||||
temp.extend(["bank_sel[{}]".format(i) for i in range(4)])
|
||||
temp.extend(["vdd", "gnd"])
|
||||
self.connect_inst(temp)
|
||||
|
||||
def route_double_msb_address(self):
|
||||
""" Route two MSB address bits and the bank decoder for 4-bank SRAM """
|
||||
|
||||
# connect the MSB flops to the address input bus
|
||||
for i in [0,1]:
|
||||
msb_pins = self.msb_address_inst.get_pins("din[{}]".format(i))
|
||||
for msb_pin in msb_pins:
|
||||
if msb_pin.layer == "metal3":
|
||||
msb_pin_pos = msb_pin.lc()
|
||||
break
|
||||
rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr[i]].x,msb_pin_pos.y)
|
||||
self.add_path("metal3",[msb_pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# Connect clk
|
||||
clk_pin = self.msb_address_inst.get_pin("clk")
|
||||
clk_pos = clk_pin.bc()
|
||||
rail_pos = self.horz_control_bus_positions["clk_buf"]
|
||||
bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
|
||||
self.add_path("metal1",[clk_pos,bend_pos,rail_pos])
|
||||
|
||||
# Connect bank decoder outputs to the bank select vertical bus wires
|
||||
for i in range(self.num_banks):
|
||||
msb_pin = self.msb_decoder_inst.get_pin("out[{}]".format(i))
|
||||
msb_pin_pos = msb_pin.lc()
|
||||
rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,msb_pin_pos.y)
|
||||
self.add_path("metal1",[msb_pin_pos,rail_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),rail_pos)
|
||||
|
||||
# connect MSB flop outputs to the bank decoder inputs
|
||||
msb_pin = self.msb_address_inst.get_pin("dout[0]")
|
||||
msb_pin_pos = msb_pin.rc()
|
||||
in_pin = self.msb_decoder_inst.get_pin("in[0]")
|
||||
in_pos = in_pin.bc() + vector(0,1*self.m2_pitch,) # pin is up from bottom
|
||||
out_pos = msb_pin_pos + vector(1*self.m2_pitch,0) # route out to the right
|
||||
up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
|
||||
self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),in_pos)
|
||||
self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
|
||||
|
||||
msb_pin = self.msb_address_inst.get_pin("dout[1]")
|
||||
msb_pin_pos = msb_pin.rc()
|
||||
in_pin = self.msb_decoder_inst.get_pin("in[1]")
|
||||
in_pos = in_pin.bc() + vector(0,self.bitcell.height+self.m2_pitch) # route the next row up
|
||||
out_pos = msb_pin_pos + vector(2*self.m2_pitch,0) # route out to the right
|
||||
up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
|
||||
self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
|
||||
self.add_via_center(("metal1","via1","metal2"),in_pos)
|
||||
self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
|
||||
|
||||
self.route_double_msb_address_supplies()
|
||||
|
||||
def route_double_msb_address_supplies(self):
|
||||
""" Route the vdd/gnd bits of the 2-bit bank decoder. """
|
||||
|
||||
# Route the right-most vdd/gnd of the right upper bank to the top of the decoder
|
||||
vdd_pins = self.bank_inst[1].get_pins("vdd")
|
||||
left_bank_vdd_pin = None
|
||||
right_bank_vdd_pin = None
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal2":
|
||||
continue
|
||||
if left_bank_vdd_pin == None or vdd_pin.lx()<left_bank_vdd_pin.lx():
|
||||
left_bank_vdd_pin = vdd_pin
|
||||
if right_bank_vdd_pin == None or vdd_pin.lx()>right_bank_vdd_pin.lx():
|
||||
right_bank_vdd_pin = vdd_pin
|
||||
# Route to top
|
||||
self.add_rect(layer="metal2",
|
||||
offset=vdd_pin.ul(),
|
||||
height=self.height-vdd_pin.uy(),
|
||||
width=vdd_pin.width())
|
||||
|
||||
gnd_pins = self.bank_inst[1].get_pins("gnd")
|
||||
left_bank_gnd_pin = None
|
||||
right_bank_gnd_pin = None
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2":
|
||||
continue
|
||||
if left_bank_gnd_pin == None or gnd_pin.lx()<left_bank_gnd_pin.lx():
|
||||
left_bank_gnd_pin = gnd_pin
|
||||
if right_bank_gnd_pin == None or gnd_pin.lx()>right_bank_gnd_pin.lx():
|
||||
right_bank_gnd_pin = gnd_pin
|
||||
# Route to top
|
||||
self.add_rect(layer="metal2",
|
||||
offset=gnd_pin.ul(),
|
||||
height=self.height-gnd_pin.uy(),
|
||||
width=gnd_pin.width())
|
||||
|
||||
# Connect bank decoder vdd/gnd supplies using the previous bank pins
|
||||
vdd_pins = self.msb_decoder_inst.get_pins("vdd")
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_vdd_pin.cx(),vdd_pin.cy())
|
||||
rail2_pos = vector(right_bank_vdd_pin.cx(),vdd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,rail2_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail2_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
gnd_pins = self.msb_decoder_inst.get_pins("gnd")
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal1":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
rail2_pos = vector(right_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,rail2_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail2_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
|
||||
# connect the bank MSB flop supplies
|
||||
vdd_pins = self.msb_address_inst.get_pins("vdd")
|
||||
# vdd pins go down to the rail
|
||||
for vdd_pin in vdd_pins:
|
||||
if vdd_pin.layer != "metal1":
|
||||
continue
|
||||
vdd_pos = vdd_pin.bc()
|
||||
down_pos = vdd_pos - vector(0,self.m1_pitch)
|
||||
rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
|
||||
self.add_path("metal1",[vdd_pos,down_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=down_pos,
|
||||
rotate=90)
|
||||
self.add_path("metal2",[down_pos,rail_pos])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail_pos)
|
||||
# gnd pins go right to the rail
|
||||
gnd_pins = self.msb_address_inst.get_pins("gnd")
|
||||
for gnd_pin in gnd_pins:
|
||||
if gnd_pin.layer != "metal2":
|
||||
continue
|
||||
rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
|
||||
self.add_path("metal1",[rail1_pos,gnd_pin.lc()])
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=gnd_pin.lc(),
|
||||
rotate=90)
|
||||
self.add_via_center(layers=("metal1","via1","metal2"),
|
||||
offset=rail1_pos,
|
||||
rotate=90,
|
||||
size=[1,3])
|
||||
|
||||
|
||||
def route(self):
|
||||
""" Route all of the signals for the four bank SRAM. """
|
||||
|
||||
self.route_shared_banks()
|
||||
|
||||
# connect the data output to the data bus
|
||||
for n in self.data_bus_names:
|
||||
for i in [0,1]:
|
||||
pin_pos = self.bank_inst[i].get_pin(n).bc()
|
||||
rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
|
||||
self.add_path("metal2",[pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
for i in [2,3]:
|
||||
pin_pos = self.bank_inst[i].get_pin(n).uc()
|
||||
rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
|
||||
self.add_path("metal2",[pin_pos,rail_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
# route msb address bits
|
||||
# route 2:4 decoder
|
||||
self.route_double_msb_address()
|
||||
|
||||
# connect the banks to the vertical address bus
|
||||
# connect the banks to the vertical control bus
|
||||
for n in self.addr_bus_names + self.control_bus_names:
|
||||
# Skip these from the horizontal bus
|
||||
if n in ["vdd", "gnd"]: continue
|
||||
# This will be the bank select, so skip it
|
||||
if n in self.msb_bank_sel_addr: continue
|
||||
|
||||
for bank_id in [0,2]:
|
||||
pin0_pos = self.bank_inst[bank_id].get_pin(n).rc()
|
||||
pin1_pos = self.bank_inst[bank_id+1].get_pin(n).lc()
|
||||
rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
|
||||
self.add_path("metal3",[pin0_pos,pin1_pos])
|
||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
||||
|
||||
|
||||
self.route_bank_supply_rails(left_banks=[0,2], bottom_banks=[2,3])
|
||||
|
||||
|
||||
Loading…
Reference in New Issue