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Increase control delay line from 4 inverters to 3 FO4 delays. Need to dynamically adjust this.

This commit is contained in:
Matt Guthaus 2018-02-07 13:10:45 -08:00
parent 5c4999d4cc
commit 3820861ce8
1 changed files with 1 additions and 1 deletions
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2
compiler/replica_bitline.py
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@ -81,7 +81,7 @@ class replica_bitline(design.design):
self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.rows)
self.add_mod(self.rbl)
self.delay_chain = self.mod_delay_chain([1, 1, 1])
self.delay_chain = self.mod_delay_chain([4, 4, 4])
self.add_mod(self.delay_chain)
self.inv = pinv()