mirror of https://github.com/VLSIDA/OpenRAM.git
Fail when using Magic/netgen for DRC/LVS. Remove arguments in running precharge test.
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09ca8ba17d
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1085497476
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@ -48,5 +48,6 @@ class precharge_test(unittest.TestCase):
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -65,7 +65,7 @@ def run_drc(name, gds_name):
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implemented in gds_name."""
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debug.warning("DRC using magic not implemented.")
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return 0
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return 1
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# the runset file contains all the options to run drc
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from tech import drc
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@ -139,7 +139,7 @@ def run_lvs(name, gds_name, sp_name):
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implemented in gds_name and sp_name. """
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debug.warning("LVS using magic+netgen not implemented.")
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return 0
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return 1
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from tech import drc
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lvs_rules = drc["lvs_rules"]
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