mirror of https://github.com/VLSIDA/OpenRAM.git
Added first test power model to sram
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@ -451,15 +451,17 @@ class delay():
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LH_slew.append(bank_delay.slew/1e3)
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HL_slew.append(bank_delay.slew/1e3)
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power = sram.analytical_power(slew, load)
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data = {"min_period": 0,
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"delay1": LH_delay,
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"delay0": HL_delay,
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"slew1": LH_slew,
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"slew0": HL_slew,
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"read0_power": 0,
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"read1_power": 0,
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"write0_power": 0,
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"write1_power": 0
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"read0_power": power,
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"read1_power": power,
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"write0_power": power,
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"write1_power": power
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}
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return data
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@ -1003,3 +1003,7 @@ class sram(design.design):
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def analytical_delay(self,slew,load):
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""" LH and HL are the same in analytical model. """
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return self.bank.analytical_delay(slew,load)
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def analytical_power(self,slew,load):
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""" Just a test function for the power."""
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return 1
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