mirror of https://github.com/VLSIDA/OpenRAM.git
making changes to bitcell_array to account for the addition nets from the multiported bitcells
This commit is contained in:
Michael Timothy Grimes
parent
820a8440c9
commit
0ea5d0b6a7
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@ -30,9 +30,18 @@ class bitcell_array(design.design):
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self.height = self.row_size*self.cell.height + drc["well_enclosure_active"]
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self.width = self.column_size*self.cell.width
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self.add_pins()
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if(OPTS.bitcell == "pbitcell"):
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self.add_multiport_pins()
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else:
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self.add_pins()
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self.create_layout()
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self.add_layout_pins()
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if(OPTS.bitcell == "pbitcell"):
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self.add_multiport_layout_pins()
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else:
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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@ -43,6 +52,25 @@ class bitcell_array(design.design):
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self.add_pin("wl[{0}]".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_multiport_pins(self):
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self.num_write = self.cell.num_write
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self.num_read = self.cell.num_read
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for col in range(self.column_size):
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for k in range(self.num_write):
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self.add_pin("wbl{0}[{1}]".format(k,col))
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self.add_pin("wbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_read):
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self.add_pin("rbl{0}[{1}]".format(k,col))
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self.add_pin("rbl_bar{0}[{1}]".format(k,col))
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for row in range(self.row_size):
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for k in range(self.num_write):
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self.add_pin("wrow{0}[{1}]".format(k,row))
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for k in range(self.num_read):
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self.add_pin("rrow{0}[{1}]".format(k,row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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xoffset = 0.0
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@ -58,16 +86,31 @@ class bitcell_array(design.design):
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(["bl[{0}]".format(col),
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"br[{0}]".format(col),
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"wl[{0}]".format(row),
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"vdd",
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"gnd"])
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if(OPTS.bitcell == "pbitcell"):
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(["wbl0[{0}]".format(col),
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"wbl_bar0[{0}]".format(col),
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"rbl0[{0}]".format(col),
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"rbl_bar0[{0}]".format(col),
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"wrow0[{0}]".format(row),
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"rrow0[{0}]".format(row),
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"vdd",
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"gnd"])
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else:
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(["bl[{0}]".format(col),
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"br[{0}]".format(col),
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"wl[{0}]".format(row),
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"vdd",
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"gnd"])
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yoffset += self.cell.height
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xoffset += self.cell.width
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@ -161,6 +204,119 @@ class bitcell_array(design.design):
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# increments to the next row height
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offset.y += self.cell.height
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def add_multiport_layout_pins(self):
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# Our cells have multiple gnd pins for now.
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# FIXME: fix for multiple vdd too
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vdd_pin = self.cell.get_pin("vdd")
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# shift it up by the overlap amount (gnd_pin) too
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# must find the lower gnd pin to determine this overlap
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lower_y = self.cell.height
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gnd_pins = self.cell.get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal2" and gnd_pin.by()<lower_y:
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lower_y=gnd_pin.by()
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# lower_y is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_height = self.height - 2*lower_y
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vdd_pin = self.cell.get_pin("vdd")
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lower_x = vdd_pin.lx()
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# lower_x is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_width = self.width - 2*lower_x
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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# get the pin of the lower row cell and make it the full width
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for k in range(self.num_write):
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wbl_pin = self.cell_inst[0,col].get_pin("wbl{0}".format(k))
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self.add_layout_pin(text="wbl{0}[{1}]".format(k,col),
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layer="metal2",
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offset=wbl_pin.ll(),
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width=wbl_pin.width(),
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height=full_height)
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wbl_bar_pin = self.cell_inst[0,col].get_pin("wbl_bar{0}".format(k))
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self.add_layout_pin(text="wbl_bar{0}[{1}]".format(k,col),
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layer="metal2",
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offset=wbl_bar_pin.ll(),
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width=wbl_bar_pin.width(),
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height=full_height)
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for k in range(self.num_read):
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rbl_pin = self.cell_inst[0,col].get_pin("rbl{0}".format(k))
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self.add_layout_pin(text="rbl{0}[{1}]".format(k,col),
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layer="metal2",
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offset=rbl_pin.ll(),
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width=rbl_pin.width(),
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height=full_height)
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rbl_bar_pin = self.cell_inst[0,col].get_pin("rbl_bar{0}".format(k))
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self.add_layout_pin(text="rbl_bar{0}[{1}]".format(k,col),
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layer="metal2",
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offset=rbl_bar_pin.ll(),
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width=rbl_bar_pin.width(),
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height=full_height)
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# gnd offset is 0 in our cell, but it be non-zero
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gnd_pins = self.cell_inst[0,col].get_pins("gnd")
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for gnd_pin in gnd_pins:
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# avoid duplicates by only doing even rows
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# also skip if it isn't the pin that spans the entire cell down to the bottom
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if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y:
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=gnd_pin.ll(),
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width=gnd_pin.width(),
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height=full_height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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vdd_pins = self.cell_inst[row,0].get_pins("vdd")
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gnd_pins = self.cell_inst[row,0].get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal1":
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add vdd label and offset
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# only add to even rows to avoid duplicates
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for vdd_pin in vdd_pins:
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if row % 2 == 0 and vdd_pin.layer=="metal1":
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add wl label and offset
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for k in range(self.num_write):
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wrow_pin = self.cell_inst[row,0].get_pin("wrow{0}".format(k))
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self.add_layout_pin(text="wrow{0}[{1}]".format(k,row),
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layer="metal1",
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offset=wrow_pin.ll(),
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width=full_width,
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height=wrow_pin.height())
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for k in range(self.num_read):
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rrow_pin = self.cell_inst[row,0].get_pin("rrow{0}".format(k))
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self.add_layout_pin(text="rrow{0}[{1}]".format(k,row),
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layer="metal1",
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offset=rrow_pin.ll(),
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width=full_width,
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height=rrow_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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def analytical_delay(self, slew, load=0):
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from tech import drc
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wl_wire = self.gen_wl_wire()
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