mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed accidental changes made to analytical delay.
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@ -716,6 +716,7 @@ class delay():
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for load in loads:
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self.set_load_slew(load,slew)
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bank_delay = sram.analytical_delay(self.slew,self.load)
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# Convert from ps to ns
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delay_lh.append(bank_delay.delay/1e3)
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delay_hl.append(bank_delay.delay/1e3)
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slew_lh.append(bank_delay.slew/1e3)
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@ -219,7 +219,7 @@ class pnor2(pgate.pgate):
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def input_load(self):
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return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"]
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def analytical_delay(self, vdd, temp, load):
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def analytical_delay(self, slew, load=0.0):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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