mirror of https://github.com/VLSIDA/OpenRAM.git
Fix control signal names on control_logic input
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@ -382,17 +382,10 @@ class sram_base(design):
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def add_control_logic(self, position):
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""" Add and place control logic """
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inputs = []
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for i in self.control_logic_inputs:
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if i != "clk":
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inputs.append(i+"_s")
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else:
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inputs.append(i)
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self.control_logic_inst=self.add_inst(name="control",
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mod=self.control_logic,
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offset=position)
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self.connect_inst(inputs + self.control_logic_outputs + ["vdd", "gnd"])
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self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"])
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