mirror of https://github.com/VLSIDA/OpenRAM.git
Add code for isdiff to output diff in tests when files mismatch.
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7d0d590879
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@ -36,4 +36,5 @@ Remove duplicate clock inverter in MS flop.
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Make lib file have delay relative to negedge for DATA. Must update
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timing code too.
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Convert characterizer into a Python package
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Convert characterizer into a Python package
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@ -4,7 +4,7 @@ Check the .lib file for an SRAM
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"""
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import unittest
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from testutils import header
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from testutils import header,isdiff
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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@ -24,7 +24,6 @@ class lib_test(unittest.TestCase):
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import sram
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import lib
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import filecmp
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debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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@ -44,7 +43,7 @@ class lib_test(unittest.TestCase):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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self.assertEqual(filecmp.cmp(libname,golden),True)
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self.assertEqual(isdiff(libname,golden),True)
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os.system("rm {0}".format(libname))
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@ -4,7 +4,7 @@ Check the LEF file for an SRMA
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"""
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import unittest
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from testutils import header
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from testutils import header,isdiff
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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@ -23,7 +23,6 @@ class lef_test(unittest.TestCase):
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import sram
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import lef
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import filecmp
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debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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@ -43,7 +42,7 @@ class lef_test(unittest.TestCase):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
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self.assertEqual(filecmp.cmp(lefname,golden),True)
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self.assertEqual(isdiff(lefname,golden),True)
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os.system("rm {0}".format(gdsname))
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os.system("rm {0}".format(lefname))
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@ -4,7 +4,7 @@ Check the .v file for an SRAM
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"""
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import unittest
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from testutils import header
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from testutils import header,isdiff
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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@ -23,7 +23,6 @@ class verilog_test(unittest.TestCase):
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import sram
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import verilog
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import filecmp
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debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram.sram(word_size=2,
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@ -41,7 +40,7 @@ class verilog_test(unittest.TestCase):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
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self.assertEqual(filecmp.cmp(vname,golden),True)
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self.assertEqual(isdiff(vname,golden),True)
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os.system("rm {0}".format(vname))
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@ -1,7 +1,7 @@
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def isclose(value1,value2,error_tolerance=1e-2):
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""" This is used to compare relative values.. """
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""" This is used to compare relative values. """
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import debug
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relative_diff = abs(value1 - value2) / max(value1,value2)
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check = relative_diff <= error_tolerance
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@ -11,6 +11,24 @@ def isclose(value1,value2,error_tolerance=1e-2):
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debug.info(2,"CLOSE {0} {1} relative diff={2}".format(value1,value2,relative_diff))
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return (check)
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def isdiff(file1,file2):
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""" This is used to compare two files and display the diff if they are different.. """
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import debug
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import filecmp
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import difflib
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check = filecmp.cmp(libname,golden)
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if not check:
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debug.info(2,"MISMATCH {0} {1}".format(file1,file2))
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f1 = open(file1,"r")
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s1 = f1.readlines()
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f2 = open(file2,"r")
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s2 = f2.readlines()
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for line in unified_diff(s1, s2):
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debug.error(line)
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else:
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debug.info(2,"MATCH {0} {1}".format(file1,file2))
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return (check)
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def header(str, tec):
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tst = "Running Test for:"
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print "\n"
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