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Fix input discrepencies in pre3x8

This commit is contained in:
Matt Guthaus 2018-01-29 15:25:41 -08:00
parent 3c5ecb963d
commit 79715ae1a2
1 changed files with 11 additions and 11 deletions
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22
compiler/hierarchical_predecode3x8.py
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@ -27,26 +27,26 @@ class hierarchical_predecode3x8(hierarchical_predecode):
self.create_rails()
self.add_input_inverters()
self.add_output_inverters()
connections=[["in[0]", "in[1]", "in[2]", "Z[7]", "vdd", "gnd"],
["in[0]", "in[1]", "inbar[2]", "Z[6]", "vdd", "gnd"],
["in[0]", "inbar[1]", "in[2]", "Z[5]", "vdd", "gnd"],
["in[0]", "inbar[1]", "inbar[2]", "Z[4]", "vdd", "gnd"],
["inbar[0]", "in[1]", "in[2]", "Z[3]", "vdd", "gnd"],
connections=[["inbar[0]", "inbar[1]", "inbar[2]", "Z[0]", "vdd", "gnd"],
["in[0]", "inbar[1]", "inbar[2]", "Z[1]", "vdd", "gnd"],
["inbar[0]", "in[1]", "inbar[2]", "Z[2]", "vdd", "gnd"],
["inbar[0]", "inbar[1]", "in[2]", "Z[1]", "vdd", "gnd"],
["inbar[0]", "inbar[1]", "inbar[2]", "Z[0]", "vdd", "gnd"]]
["in[0]", "in[1]", "inbar[2]", "Z[3]", "vdd", "gnd"],
["inbar[0]", "inbar[1]", "in[2]", "Z[4]", "vdd", "gnd"],
["in[0]", "inbar[1]", "in[2]", "Z[5]", "vdd", "gnd"],
["inbar[0]", "in[1]", "in[2]", "Z[6]", "vdd", "gnd"],
["in[0]", "in[1]", "in[2]", "Z[7]", "vdd", "gnd"]]
self.add_nand(connections)
self.route()
def get_nand_input_line_combination(self):
""" These are the decoder connections of the NAND gates to the A,B,C pins """
combination = [["Abar[0]", "Abar[1]", "Abar[2]"],
["Abar[0]", "Abar[1]", "A[2]"],
["Abar[0]", "A[1]", "Abar[2]"],
["Abar[0]", "A[1]", "A[2]"],
["A[0]", "Abar[1]", "Abar[2]"],
["A[0]", "Abar[1]", "A[2]"],
["Abar[0]", "A[1]", "Abar[2]"],
["A[0]", "A[1]", "Abar[2]"],
["Abar[0]", "Abar[1]", "A[2]"],
["A[0]", "Abar[1]", "A[2]"],
["Abar[0]", "A[1]", "A[2]"],
["A[0]", "A[1]", "A[2]"]]
return combination