mirror of https://github.com/VLSIDA/OpenRAM.git
Fix ngspice scnmos results
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@ -56,10 +56,10 @@ class timing_sram_test(unittest.TestCase):
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self.assertTrue(isclose(data['min_period1'],0.078582763671875)) # diff than hspice
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self.assertTrue(isclose(data['min_period0'],0.25543212890625)) # diff than hspice
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elif OPTS.tech_name == "scn3me_subm":
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self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice
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self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice
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self.assertTrue(isclose(data['min_period1'],1.6650390625)) # diff than hspice
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self.assertTrue(isclose(data['min_period0'],1.25244140625)) # diff than hspice
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self.assertTrue(isclose(data['delay1'],1.5342000000000002)) # diff than hspice
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self.assertTrue(isclose(data['delay0'],2.2698)) # diff than hspice
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self.assertTrue(isclose(data['min_period1'],1.534423828125)) # diff than hspice
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self.assertTrue(isclose(data['min_period0'],2.99560546875)) # diff than hspice
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else:
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self.assertTrue(False) # other techs fail
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