mirror of https://github.com/VLSIDA/OpenRAM.git
Clean up Python comments and improve comments in stimulus file.
This commit is contained in:
Matt Guthaus
parent
3820861ce8
commit
3e4ef36efe
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@ -10,7 +10,7 @@ from globals import OPTS
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class delay():
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"""
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Functions to measure the delay of the SRAM at a given address and
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Functions to measure the delay of an SRAM at a given address and
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data bit.
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"""
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@ -52,7 +52,7 @@ class delay():
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# creates and opens stimulus file for writing
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(period,load,slew))
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self.sf.write("\n* Stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(period,load,slew))
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# include files in stimulus file
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model_list = tech.spice["fet_models"] + [self.sram_sp_file]
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@ -60,26 +60,26 @@ class delay():
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# add vdd/gnd statements
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self.sf.write("* Global Power Supplies\n")
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self.sf.write("\n* Global Power Supplies\n")
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stimuli.write_supply(self.sf)
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# instantiate the sram
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self.sf.write("* Instantiation of the SRAM\n")
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self.sf.write("\n* Instantiation of the SRAM\n")
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stimuli.inst_sram(stim_file=self.sf,
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abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.sf.write("* SRAM output loads\n")
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self.sf.write("\n* SRAM output loads\n")
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for i in range(self.word_size):
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self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load))
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# add access transistors for data-bus
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self.sf.write("* Transmission Gates for data-bus and control signals\n")
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self.sf.write("\n* Transmission Gates for data-bus and control signals\n")
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stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size)
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# generate data and addr signals
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self.sf.write("* Generation of data and address signals\n")
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self.sf.write("\n* Generation of data and address signals\n")
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for i in range(self.word_size):
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if i == self.probe_data:
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self.gen_data(clk_times=self.cycle_times,
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@ -97,20 +97,20 @@ class delay():
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slew=slew)
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# generate control signals
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self.sf.write("* Generation of control signals\n")
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self.sf.write("\n* Generation of control signals\n")
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self.gen_csb(self.cycle_times, period, slew)
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self.gen_web(self.cycle_times, period, slew)
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self.gen_oeb(self.cycle_times, period, slew)
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self.sf.write("* Generation of global clock signal\n")
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self.sf.write("\n* Generation of global clock signal\n")
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stimuli.gen_pulse(stim_file=self.sf,
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sig_name="CLK",
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v1=self.gnd,
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v2=self.vdd,
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offset=period,
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period=period,
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t_rise = slew,
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t_fall = slew)
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t_rise=slew,
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t_fall=slew)
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self.write_measures(period)
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@ -120,17 +120,23 @@ class delay():
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self.sf.close()
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def write_measures(self,period):
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# meas statement for delay and power measurements
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self.sf.write("* Measure statements for delay and power\n")
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"""
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Write the measure statements to quantify the delay and power results.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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# what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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# Trigger on the clk of the appropriate cycle
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trig_name = "clk"
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targ_name = "{0}".format("d[{0}]".format(self.probe_data))
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trig_val = targ_val = 0.5 * self.vdd
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# add measure statments for delay0
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# delay the target to measure after the negative edge
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# Delay the target to measure after the negative edge
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stimuli.gen_meas_delay(stim_file=self.sf,
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meas_name="DELAY0",
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trig_name=trig_name,
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@ -205,11 +211,13 @@ class delay():
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t_final=t_final)
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def find_feasible_period(self, load, slew):
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"""Uses an initial period and finds a feasible period before we
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"""
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Uses an initial period and finds a feasible period before we
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run the binary search algorithm to find min period. We check if
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the given clock period is valid and if it's not, we continue to
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double the period until we find a valid period to use as a
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starting point. """
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starting point.
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"""
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feasible_period = tech.spice["feasible_period"]
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time_out = 8
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@ -225,13 +233,20 @@ class delay():
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feasible_period = 2 * feasible_period
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continue
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debug.info(1, "Found feasible_period: {0}ns feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,feasible_delay1,feasible_delay0,feasible_slew1,feasible_slew0))
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debug.info(1, "Found feasible_period: {0}ns " +
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"feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
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feasible_delay1,
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feasible_delay0,
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feasible_slew1,
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feasible_slew0))
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return (feasible_period, feasible_delay1, feasible_delay0)
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def run_simulation(self, period, load, slew):
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""" This tries to simulate a period and checks if the result
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works. If so, it returns True and the delays and slews."""
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"""
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This tries to simulate a period and checks if the result
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works. If so, it returns True and the delays and slews.
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"""
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# Checking from not data_value to data_value
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self.write_stimulus(period, load, slew)
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@ -243,17 +258,40 @@ class delay():
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# if it failed or the read was longer than a period
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if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float:
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debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1))
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debug.info(2,"Failed simulation: period {0} load {1} slew {2}, " +
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"delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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return (False,0,0,0,0)
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# Scale delays to ns (they previously could have not been floats)
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delay0 *= 1e9
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delay1 *= 1e9
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slew0 *= 1e9
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slew1 *= 1e9
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if delay0>period or delay1>period or slew0>period or slew1>period:
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debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1))
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debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, " +
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"delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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return (False,0,0,0,0)
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else:
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debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1))
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debug.info(2,"Successful simulation: period {0} load {1} slew {2}, " +
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"delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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# For debug, you sometimes want to inspect each simulation.
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#key=raw_input("press return to continue")
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# The delay is from the negative edge for our SRAM
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@ -262,8 +300,10 @@ class delay():
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def find_min_period(self,feasible_period, load, slew, feasible_delay1, feasible_delay0):
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"""Searches for the smallest period with output delays being within 5% of
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long period. """
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"""
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Searches for the smallest period with output delays being within 5% of
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long period.
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"""
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previous_period = ub_period = feasible_period
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lb_period = 0.0
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@ -291,8 +331,10 @@ class delay():
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def try_period(self, period, load, slew, feasible_delay1, feasible_delay0):
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""" This tries to simulate a period and checks if the result
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works. If it does and the delay is within 5% still, it returns True."""
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"""
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This tries to simulate a period and checks if the result
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works. If it does and the delay is within 5% still, it returns True.
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"""
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# Checking from not data_value to data_value
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self.write_stimulus(period,load,slew)
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@ -303,14 +345,16 @@ class delay():
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slew1 = ch.convert_to_float(ch.parse_output("timing", "slew1"))
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# if it failed or the read was longer than a period
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if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float:
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debug.info(2,"Invalid measures: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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debug.info(2,"Invalid measures: Period {0}, " +
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"delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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return False
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delay0 *= 1e9
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delay1 *= 1e9
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slew0 *= 1e9
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slew1 *= 1e9
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if delay0>period or delay1>period or slew0>period or slew1>period:
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debug.info(2,"Too long delay/slew: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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debug.info(2,"Too long delay/slew: Period {0}, " +
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"delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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return False
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else:
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if not ch.relative_compare(delay1,feasible_delay1,error_tolerance=0.05):
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@ -323,7 +367,8 @@ class delay():
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#key=raw_input("press return to continue")
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debug.info(2,"Successful period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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debug.info(2,"Successful period {0}, " +
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"delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1))
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return True
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def set_probe(self,probe_address, probe_data):
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@ -520,7 +565,7 @@ class delay():
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return data
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def gen_data(self, clk_times, sig_name, period, slew):
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"""Generates the PWL data inputs for a simulation timing test."""
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""" Generates the PWL data inputs for a simulation timing test. """
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# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
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# we are asserting the opposite value on the other side of the tx gate during
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# the read to be "worst case". Otherwise, it can actually assist the read.
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@ -528,8 +573,9 @@ class delay():
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stimuli.gen_pwl(self.sf, sig_name, clk_times, values, period, slew, 0.05)
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def gen_addr(self, clk_times, addr, period, slew):
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"""Generates the address inputs for a simulation timing test.
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One cycle is different to clear the bus
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"""
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Generates the address inputs for a simulation timing test.
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This alternates between all 1's and all 0's for the address.
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"""
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zero_values = [0, 0, 0, 1, 0, 0, 0, 1, 0, 0 ]
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@ -544,14 +590,14 @@ class delay():
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def gen_csb(self, clk_times, period, slew):
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""" Generates the PWL CSb signal"""
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""" Generates the PWL CSb signal """
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# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
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# Keep CSb asserted in NOP for measuring >1 period
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values = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0]
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stimuli.gen_pwl(self.sf, "csb", clk_times, values, period, slew, 0.05)
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def gen_web(self, clk_times, period, slew):
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""" Generates the PWL WEb signal"""
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""" Generates the PWL WEb signal """
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# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
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# Keep WEb deasserted in NOP for measuring >1 period
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values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1]
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@ -564,7 +610,7 @@ class delay():
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stimuli.gen_pwl(self.sf, "acc_en_inv", clk_times, values, period, slew, 0)
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def gen_oeb(self, clk_times, period, slew):
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""" Generates the PWL WEb signal"""
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""" Generates the PWL WEb signal """
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# values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP
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# Keep OEb asserted in NOP for measuring >1 period
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values = [1, 1, 1, 1, 0, 0, 1, 1, 0, 0]
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@ -1,7 +1,7 @@
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"""
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This file generates the test structure and stimulus for an sram
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simulation. There are various functions that can be be used to
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generate stimulus for other simulations as well.
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This file generates simple spice cards for simulation. There are
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various functions that can be be used to generate stimulus for other
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simulations as well.
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"""
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import tech
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@ -22,7 +22,7 @@ tx_width = tech.spice["minwidth_tx"]
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tx_length = tech.spice["channel"]
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def inst_sram(stim_file, abits, dbits, sram_name):
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"""function to instatiate the sram subckt"""
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""" Function to instatiate an SRAM subckt. """
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stim_file.write("Xsram ")
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for i in range(dbits):
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stim_file.write("D[{0}] ".format(i))
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@ -32,11 +32,11 @@ def inst_sram(stim_file, abits, dbits, sram_name):
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stim_file.write("{0} ".format(i))
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stim_file.write("{0} ".format(tech.spice["clk"]))
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stim_file.write("{0} {1} ".format(vdd_name, gnd_name))
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stim_file.write("{0}\n\n".format(sram_name))
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stim_file.write("{0}\n".format(sram_name))
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def inst_model(stim_file, pins, model_name):
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"""function to instantiate a model"""
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""" Function to instantiate a generic model with a set of pins """
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stim_file.write("X{0} ".format(model_name))
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for pin in pins:
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stim_file.write("{0} ".format(pin))
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@ -44,7 +44,7 @@ def inst_model(stim_file, pins, model_name):
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def create_inverter(stim_file, size=1, beta=2.5):
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"""Generates inverter for the top level signals (only for sim purposes)"""
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""" Generates inverter for the top level signals (only for sim purposes) """
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stim_file.write(".SUBCKT test_inv in out {0} {1}\n".format(vdd_name, gnd_name))
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stim_file.write("mpinv out in {0} {0} {1} w={2}u l={3}u\n".format(vdd_name,
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pmos_name,
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@ -58,9 +58,10 @@ def create_inverter(stim_file, size=1, beta=2.5):
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def create_buffer(stim_file, buffer_name, size=[1,3], beta=2.5):
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"""Generates buffer for top level signals (only for sim
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purposes). Size is pair for PMOS, NMOS width multiple. It includes
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a beta of 3."""
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"""
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Generates buffer for top level signals (only for sim
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purposes). Size is pair for PMOS, NMOS width multiple.
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"""
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stim_file.write(".SUBCKT test_{2} in out {0} {1}\n".format(vdd_name,
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gnd_name,
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@ -85,7 +86,7 @@ def create_buffer(stim_file, buffer_name, size=[1,3], beta=2.5):
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def inst_buffer(stim_file, buffer_name, signal_list):
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"""Adds buffers to each top level signal that is in signal_list (only for sim purposes)"""
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""" Adds buffers to each top level signal that is in signal_list (only for sim purposes) """
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for signal in signal_list:
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stim_file.write("X{0}_buffer {0} {0}_buf {1} {2} test_{3}\n".format(signal,
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"test"+vdd_name,
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@ -94,7 +95,7 @@ def inst_buffer(stim_file, buffer_name, signal_list):
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def inst_inverter(stim_file, signal_list):
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"""Adds inv for each signal that needs its inverted version (only for sim purposes)"""
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""" Adds inv for each signal that needs its inverted version (only for sim purposes) """
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for signal in signal_list:
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stim_file.write("X{0}_inv {0} {0}_inv {1} {2} test_inv\n".format(signal,
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"test"+vdd_name,
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@ -102,7 +103,7 @@ def inst_inverter(stim_file, signal_list):
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def inst_accesstx(stim_file, dbits):
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"""Adds transmission gate for inputs to data-bus (only for sim purposes)"""
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""" Adds transmission gate for inputs to data-bus (only for sim purposes) """
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stim_file.write("* Tx Pin-list: Drain Gate Source Body\n")
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for i in range(dbits):
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pmos_access_string="mp{0} DATA[{0}] acc_en D[{0}] {1} {2} w={3}u l={4}u\n"
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@ -119,8 +120,11 @@ def inst_accesstx(stim_file, dbits):
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tx_length))
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def gen_pulse(stim_file, sig_name, v1=gnd_voltage, v2=vdd_voltage, offset=0, period=1, t_rise=0, t_fall=0):
|
||||
"""Generates a periodic signal with 50% duty cycle and slew rates. Period is measured
|
||||
from 50% to 50%."""
|
||||
"""
|
||||
Generates a periodic signal with 50% duty cycle and slew rates. Period is measured
|
||||
from 50% to 50%.
|
||||
"""
|
||||
stim_file.write("* PULSE: period={0}\n".format(period))
|
||||
pulse_string="V{0} {0} 0 PULSE ({1} {2} {3}n {4}n {5}n {6}n {7}n)\n"
|
||||
stim_file.write(pulse_string.format(sig_name,
|
||||
v1,
|
||||
|
|
@ -133,6 +137,11 @@ def gen_pulse(stim_file, sig_name, v1=gnd_voltage, v2=vdd_voltage, offset=0, per
|
|||
|
||||
|
||||
def gen_pwl(stim_file, sig_name, clk_times, data_values, period, slew, setup):
|
||||
"""
|
||||
Generate a PWL stimulus given a signal name and data values at each period.
|
||||
Automatically creates slews and ensures each data occurs a setup before the clock
|
||||
edge.
|
||||
"""
|
||||
# the initial value is not a clock time
|
||||
debug.check(len(clk_times)==len(data_values),"Clock and data value lengths don't match.")
|
||||
|
||||
|
|
@ -140,6 +149,7 @@ def gen_pwl(stim_file, sig_name, clk_times, data_values, period, slew, setup):
|
|||
times = np.array(clk_times) - setup*period
|
||||
values = np.array(data_values) * vdd_voltage
|
||||
half_slew = 0.5 * slew
|
||||
stim_file.write("* (time, data): {}\n".format(zip(clk_times, data_values)))
|
||||
stim_file.write("V{0} {0} 0 PWL (0n {1}v ".format(sig_name, values[0]))
|
||||
for i in range(1,len(times)-1):
|
||||
stim_file.write("{0}n {1}v {2}n {3}v ".format(times[i]-half_slew,
|
||||
|
|
@ -148,13 +158,10 @@ def gen_pwl(stim_file, sig_name, clk_times, data_values, period, slew, setup):
|
|||
values[i]))
|
||||
stim_file.write(")\n")
|
||||
|
||||
|
||||
def gen_constant(stim_file, sig_name, v_val):
|
||||
"""Generates a constant signal with reference voltage and the voltage value"""
|
||||
""" Generates a constant signal with reference voltage and the voltage value """
|
||||
stim_file.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val))
|
||||
|
||||
|
||||
|
||||
def get_inverse_voltage(value):
|
||||
if value > 0.5*vdd_voltage:
|
||||
return gnd_voltage
|
||||
|
|
@ -173,7 +180,7 @@ def get_inverse_value(value):
|
|||
|
||||
|
||||
def gen_meas_delay(stim_file, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td):
|
||||
"""Creates the .meas statement for the measurement of delay"""
|
||||
""" Creates the .meas statement for the measurement of delay """
|
||||
measure_string=".meas tran {0} TRIG v({1}) VAL={2} {3}=1 TD={4}n TARG v({5}) VAL={6} {7}=1 TD={8}n\n\n"
|
||||
stim_file.write(measure_string.format(meas_name,
|
||||
trig_name,
|
||||
|
|
@ -186,7 +193,7 @@ def gen_meas_delay(stim_file, meas_name, trig_name, targ_name, trig_val, targ_va
|
|||
targ_td))
|
||||
|
||||
def gen_meas_power(stim_file, meas_name, t_initial, t_final):
|
||||
"""Creates the .meas statement for the measurement of avg power"""
|
||||
""" Creates the .meas statement for the measurement of avg power """
|
||||
# power mea cmd is different in different spice:
|
||||
if OPTS.spice_name == "hspice":
|
||||
power_exp = "power"
|
||||
|
|
@ -196,9 +203,9 @@ def gen_meas_power(stim_file, meas_name, t_initial, t_final):
|
|||
power_exp,
|
||||
t_initial,
|
||||
t_final))
|
||||
stim_file.write("\n")
|
||||
|
||||
def write_control(stim_file, end_time):
|
||||
""" Write the control cards to run and end the simulation """
|
||||
# UIC is needed for ngspice to converge
|
||||
stim_file.write(".TRAN 5p {0}n UIC\n".format(end_time))
|
||||
if OPTS.spice_name == "ngspice":
|
||||
|
|
@ -227,22 +234,22 @@ def write_include(stim_file, models):
|
|||
"""Writes include statements, inputs are lists of model files"""
|
||||
for item in list(models):
|
||||
if os.path.isfile(item):
|
||||
stim_file.write(".include \"{0}\"\n\n".format(item))
|
||||
stim_file.write(".include \"{0}\"\n".format(item))
|
||||
else:
|
||||
debug.error("Could not find spice model: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item))
|
||||
|
||||
|
||||
def write_supply(stim_file):
|
||||
"""Writes supply voltage statements"""
|
||||
""" Writes supply voltage statements """
|
||||
stim_file.write("V{0} {0} 0.0 {1}\n".format(vdd_name, vdd_voltage))
|
||||
stim_file.write("V{0} {0} 0.0 {1}\n".format(gnd_name, gnd_voltage))
|
||||
# This is for the test power supply
|
||||
stim_file.write("V{0} {0} 0.0 {1}\n".format("test"+vdd_name, vdd_voltage))
|
||||
stim_file.write("V{0} {0} 0.0 {1}\n\n".format("test"+gnd_name, gnd_voltage))
|
||||
stim_file.write("V{0} {0} 0.0 {1}\n".format("test"+gnd_name, gnd_voltage))
|
||||
|
||||
|
||||
def run_sim():
|
||||
"""Run hspice in batch mode and output rawfile to parse."""
|
||||
""" Run hspice in batch mode and output rawfile to parse. """
|
||||
temp_stim = "{0}stim.sp".format(OPTS.openram_temp)
|
||||
import datetime
|
||||
start_time = datetime.datetime.now()
|
||||
|
|
|
|||
Loading…
Reference in New Issue