mirror of https://github.com/VLSIDA/OpenRAM.git
Convert period to float to avoid type mismatch.
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132c91d68f
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322f354878
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@ -299,7 +299,7 @@ class delay():
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starting point.
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"""
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feasible_period = tech.spice["feasible_period"]
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feasible_period = float(tech.spice["feasible_period"])
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time_out = 8
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while True:
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debug.info(1, "Trying feasible period: {0}ns".format(feasible_period))
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@ -317,11 +317,11 @@ class delay():
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feasible_delay_hl = results["delay_hl"]
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feasible_slew_hl = results["slew_hl"]
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debug.info(1, "Found feasible_period: {0}ns feasible_delay_lh/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
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feasible_delay_lh,
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feasible_delay_hl,
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feasible_slew_lh,
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feasible_slew_hl))
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debug.info(1, "Found feasible_period: {0}ns feasible_delay {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
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feasible_delay_lh,
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feasible_delay_hl,
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feasible_slew_lh,
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feasible_slew_hl))
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self.period = feasible_period
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return (feasible_delay_lh, feasible_delay_hl)
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