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changing pbitcell_array test to include an important permutation of the design

This commit is contained in:
Michael Timothy Grimes 2018-07-12 23:45:47 -07:00
parent 7b315a3b69
commit a64ca423c6
1 changed files with 8 additions and 1 deletions
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9
compiler/tests/05_pbitcell_array_test.py Executable file → Normal file
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@ -36,10 +36,17 @@ class array_multiport_test(openram_test):
OPTS.r_ports = 0
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.rw_ports = 2
OPTS.r_ports = 0
OPTS.w_ports = 0
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.bitcell = "bitcell"
OPTS.check_lvsdrc = True