mirror of https://github.com/VLSIDA/OpenRAM.git
resolved conflicts with bitcell_array after PrivateRAM merge
This commit is contained in:
Michael Timothy Grimes
parent
b5df0cc30a
commit
5e4d4bf6cd
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@ -1,201 +1,202 @@
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import debug
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import design
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from tech import drc, spice
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from vector import vector
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from globals import OPTS
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class bitcell_array(design.design):
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"""
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Creates a rows x cols array of memory cells. Assumes bit-lines
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and word line is connected by abutment.
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Connects the word lines and bit lines.
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"""
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def __init__(self, cols, rows, name="bitcell_array"):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.column_size = cols
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self.row_size = rows
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.cell = self.mod_bitcell()
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self.add_mod(self.cell)
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height + drc["well_enclosure_active"]
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self.width = self.column_size*self.cell.width
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self.add_pins()
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self.create_layout()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin(cell_column+"[{0}]".format(col))
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin(cell_row+"[{0}]".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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xoffset = 0.0
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self.cell_inst = {}
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for col in range(self.column_size):
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yoffset = 0.0
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if row % 2:
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tempy = yoffset + self.cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(self.cell.list_bitcell_pins(col, row))
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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# Our cells have multiple gnd pins for now.
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# FIXME: fix for multiple vdd too
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vdd_pin = self.cell.get_pin("vdd")
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# shift it up by the overlap amount (gnd_pin) too
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# must find the lower gnd pin to determine this overlap
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lower_y = self.cell.height
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gnd_pins = self.cell.get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal2" and gnd_pin.by()<lower_y:
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lower_y=gnd_pin.by()
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# lower_y is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_height = self.height - 2*lower_y
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vdd_pin = self.cell.get_pin("vdd")
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lower_x = vdd_pin.lx()
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# lower_x is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_width = self.width - 2*lower_x
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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# get the pins of the lower row cell and make it the full width
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"[{0}]".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=full_height)
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# gnd offset is 0 in our cell, but it be non-zero
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gnd_pins = self.cell_inst[0,col].get_pins("gnd")
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for gnd_pin in gnd_pins:
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# avoid duplicates by only doing even rows
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# also skip if it isn't the pin that spans the entire cell down to the bottom
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if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y:
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=gnd_pin.ll(),
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width=gnd_pin.width(),
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height=full_height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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vdd_pins = self.cell_inst[row,0].get_pins("vdd")
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gnd_pins = self.cell_inst[row,0].get_pins("gnd")
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# add wl label and offset
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"[{0}]".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=full_width,
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height=wl_pin.height())
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal1":
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add vdd label and offset
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# only add to even rows to avoid duplicates
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for vdd_pin in vdd_pins:
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if row % 2 == 0 and vdd_pin.layer=="metal1":
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# increments to the next row height
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offset.y += self.cell.height
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def analytical_delay(self, slew, load=0):
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from tech import drc
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wl_wire = self.gen_wl_wire()
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wl_wire.return_delay_over_wire(slew)
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wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
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# hypothetical delay from cell to bl end without sense amp
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
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# hence just use the whole c
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bl_swing = 0.1
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cell_delay = self.cell.analytical_delay(wl_to_cell_delay.slew, cell_load, swing = bl_swing)
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#we do not consider the delay over the wire for now
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return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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wl_to_cell_delay.slew)
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def gen_wl_wire(self):
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wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc["minwidth_metal1"])
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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import debug
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import design
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from tech import drc, spice
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from vector import vector
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from globals import OPTS
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class bitcell_array(design.design):
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"""
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Creates a rows x cols array of memory cells. Assumes bit-lines
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and word line is connected by abutment.
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Connects the word lines and bit lines.
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"""
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def __init__(self, cols, rows, name="bitcell_array"):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.column_size = cols
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self.row_size = rows
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#from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.cell = self.mod_bitcell()
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self.add_mod(self.cell)
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height + drc["well_enclosure_active"] + self.m1_width
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self.width = self.column_size*self.cell.width + self.m1_width
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self.add_pins()
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self.create_layout()
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self.add_layout_pins()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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#self.offset_all_coordinates()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin(cell_column+"[{0}]".format(col))
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin(cell_row+"[{0}]".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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xoffset = 0.0
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self.cell_inst = {}
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for col in range(self.column_size):
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yoffset = 0.0
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if row % 2:
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tempy = yoffset + self.cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(self.cell.list_bitcell_pins(col, row))
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"[{0}]".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"[{0}]".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=self.width,
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height=wl_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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# For every second row and column, add a via for vdd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for vdd_pin in inst.get_pins("vdd"):
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# Drop to M1 if needed
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if vdd_pin.layer == "metal1":
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vdd_pin.center(),
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rotate=90)
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# Always drop to M2
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pin.center())
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pin.center())
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# For every second row and column (+1), add a via for gnd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for gnd_pin in inst.get_pins("gnd"):
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# Drop to M1 if needed
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if gnd_pin.layer == "metal1":
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=gnd_pin.center(),
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rotate=90)
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# Always drop to M2
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=gnd_pin.center())
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal3",
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offset=gnd_pin.center())
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def analytical_delay(self, slew, load=0):
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from tech import drc
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wl_wire = self.gen_wl_wire()
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wl_wire.return_delay_over_wire(slew)
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wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
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# hypothetical delay from cell to bl end without sense amp
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
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# hence just use the whole c
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bl_swing = 0.1
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cell_delay = self.cell.analytical_delay(wl_to_cell_delay.slew, cell_load, swing = bl_swing)
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#we do not consider the delay over the wire for now
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return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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wl_to_cell_delay.slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = 0.1 #This should probably be defined in the tech file or input
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freq = spice["default_event_rate"]
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bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
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#Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(proc, vdd, temp, load)
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#Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc["minwidth_metal1"])
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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