mirror of https://github.com/VLSIDA/OpenRAM.git
Add new supplies to replica bitline
This commit is contained in:
Matt Guthaus
parent
3bbb604504
commit
93e830e800
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@ -42,8 +42,8 @@ class replica_bitline(design.design):
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#self.add_lvs_correspondence_points()
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self.width = self.right_gnd_pin.rx() - self.left_gnd_pin.lx()
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self.height = self.left_gnd_pin.uy() - self.left_gnd_pin.by()
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self.width = self.rbl_inst.rx() - self.dc_inst.lx()
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self.height = max(self.rbl_inst.uy(), self.dc_inst.uy())
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self.DRC_LVS()
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@ -126,25 +126,54 @@ class replica_bitline(design.design):
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def route(self):
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""" Connect all the signals together """
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self.route_vdd()
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self.route_gnd()
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self.route_vdd_gnd()
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self.route_supplies()
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self.route_wl()
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self.route_access_tx()
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def route_vdd_gnd(self):
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def route_wl(self):
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""" Connect the RBL word lines to gnd """
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# Connect the WL and gnd pins directly to the center and right gnd rails
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for row in range(self.bitcell_loads):
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wl = "wl[{}]".format(row)
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pin = self.rbl_inst.get_pin(wl)
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if pin.layer != "metal1":
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continue
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self.add_power_pin("gnd", pin.center())
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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# These are the instances that every bank has
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top_instances = [self.rbl_inst,
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self.rbl_inv_inst,
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self.rbc_inst,
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self.dc_inst]
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self.dc_inst]
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for inst in top_instances:
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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# Route the inverter supply pin from M1
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# Only vdd is needed because gnd shares a rail with the delay chain
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pin = self.rbl_inv_inst.get_pin("vdd")
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self.add_power_pin("vdd", pin.lc())
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# Replica bitcell and the inverter need to be routed up to M3
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for pin_name in ["vdd", "gnd"]:
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for pin in self.rbc_inst.get_pins(pin_name):
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# Drop to M1 if needed
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if pin.layer == "metal1":
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pin.center(),
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rotate=90)
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# Always drop to M2
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin.center())
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self.add_layout_pin_rect_center(text=pin_name,
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layer="metal3",
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offset=pin.center())
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def route_access_tx(self):
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# GATE ROUTE
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# 1. Add the poly contact and nwell enclosure
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@ -183,7 +212,7 @@ class replica_bitline(design.design):
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# DRAIN ROUTE
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# Route the drain to the vdd rail
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drain_offset = self.tx_inst.get_pin("D").center()
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self.add_path("metal1", [drain_offset, drain_offset.scale(1,0)])
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self.add_power_pin("vdd", drain_offset)
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# SOURCE ROUTE
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# Route the drain to the RBL inverter input
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@ -194,13 +223,11 @@ class replica_bitline(design.design):
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# Route the connection of the source route to the RBL bitline (left)
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# Via will go halfway down from the bitcell
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bl_offset = self.rbc_inst.get_pin("BL").bc()
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self.add_path("metal3",[source_offset, bl_offset])
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# Route down a pitch so we can use M2 routing
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bl_down_offset = bl_offset - vector(0, self.m2_pitch)
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self.add_path("metal2",[source_offset, bl_down_offset, bl_offset])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=source_offset)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=source_offset)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=bl_offset)
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# BODY ROUTE
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# Connect it to the inverter well
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@ -213,30 +240,10 @@ class replica_bitline(design.design):
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def route_vdd(self):
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""" Route all signals connected to vdd """
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self.copy_layout_pin(self.dc_inst,"vdd")
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self.copy_layout_pin(self.rbc_inst,"vdd")
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# Route the vdd lines from left to right
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# Add via for the delay chain
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left_vdd_start = self.dc_inst.ll().scale(1,0) - vector(self.m2_pitch,0)
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left_vdd_end = vector(left_vdd_start.x, self.rbl_inst.uy())
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self.left_vdd_pin=self.add_segment_center(layer="metal2",
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start=left_vdd_start,
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end=left_vdd_end)
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# Vdd line to the left of the replica bitline
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center_vdd_start = self.rbc_inst.ll() - vector(3*self.m2_pitch,0)
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center_vdd_end = vector(center_vdd_start.x, self.rbl_inst.uy())
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self.center_vdd_pin=self.add_segment_center(layer="metal2",
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start=center_vdd_start,
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end=center_vdd_end)
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# Vdd line to the right of the replica bitline
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right_vdd_start = self.rbc_inst.lr() + vector(2*self.m2_pitch,0)
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right_vdd_end = vector(right_vdd_start.x, self.rbl_inst.uy())
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self.right_vdd_pin=self.add_segment_center(layer="metal2",
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start=right_vdd_start,
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end=right_vdd_end)
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# Connect the WL and vdd pins directly to the center and right vdd rails
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@ -260,24 +267,6 @@ class replica_bitline(design.design):
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# Connect the vdd pins of the delay chain to the left rails
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dc_vdd_pins = self.dc_inst.get_pins("vdd")
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for pin in dc_vdd_pins:
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if pin.layer != "metal1":
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continue
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start = vector(self.left_vdd_pin.cx(),pin.cy())
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# Note, we don't connect to center because of via conflicts
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# with the RBL pins
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#end = vector(center_vdd_pin.cx(),pin.cy())
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end = pin.rc()
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self.add_layout_pin_segment_center(text="vdd",
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layer="metal1",
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start=start,
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end=end)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start,
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rotate=90)
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# Add via for the inverter
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pin = self.rbl_inv_inst.get_pin("vdd")
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