mirror of https://github.com/VLSIDA/OpenRAM.git
Document tech files. Remove unused/redundant rules. Made rule names consistent/simple.
This commit is contained in:
Matt Guthaus
parent
fd748b4fe4
commit
e95988c639
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@ -56,14 +56,14 @@ class contact(design.design):
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drc["{0}_enclosure_{1}".format(self.first_layer_name, self.via_layer_name)])
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self.first_layer_vertical_enclosure = max(utils.ceil((drc["minarea_{0}".format(self.first_layer_name)]
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/ (self.contact_array_width + 2 * self.first_layer_horizontal_enclosure) - self.contact_array_height) / 2),
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(drc["minheight_{0}".format(self.first_layer_name)] - self.contact_array_height) / 2,
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(drc["minwidth_{0}".format(self.first_layer_name)] - self.contact_array_height) / 2,
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drc["{0}_extend_{1}".format(self.first_layer_name, self.via_layer_name)])
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self.second_layer_horizontal_enclosure = max((drc["minwidth_{0}".format(self.second_layer_name)] - self.contact_array_width) / 2,
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drc["{0}_enclosure_{1}".format(self.second_layer_name, self.via_layer_name)])
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self.second_layer_vertical_enclosure = max(utils.ceil((drc["minarea_{0}".format(self.second_layer_name)]
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/ (self.contact_array_width + 2 * self.second_layer_horizontal_enclosure) - self.contact_array_height) / 2),
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(drc["minheight_{0}".format(self.second_layer_name)] - self.contact_array_height) / 2,
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(drc["minwidth_{0}".format(self.second_layer_name)] - self.contact_array_height) / 2,
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drc["{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name)])
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# offset for the via array
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self.via_layer_position =vector(max(self.first_layer_horizontal_enclosure,self.second_layer_horizontal_enclosure),
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@ -102,17 +102,17 @@ class ptx(design.design):
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self.poly_extend_active = drc["poly_extend_active"]
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# The contacted poly pitch (or uncontacted in an odd technology)
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self.poly_pitch = max(2*drc["contact_to_poly"] + self.contact_width + self.poly_width,
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self.poly_pitch = max(2*drc["contact_to_gate"] + self.contact_width + self.poly_width,
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drc["poly_to_poly"])
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# The contacted poly pitch (or uncontacted in an odd technology)
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self.contact_pitch = 2*drc["contact_to_poly"] + self.contact_width + self.poly_width
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self.contact_pitch = 2*drc["contact_to_gate"] + self.contact_width + self.poly_width
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# The enclosure of an active contact. Not sure about second term.
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active_enclose_contact = max(drc["active_enclosure_contact"],
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(self.min_active_width - self.contact_width)/2)
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# This is the distance from the edge of poly to the contacted end of active
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self.end_to_poly = active_enclose_contact + self.contact_width + drc["contact_to_poly"]
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self.end_to_poly = active_enclose_contact + self.contact_width + drc["contact_to_gate"]
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# Active width is determined by enclosure on both ends and contacted pitch,
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@ -80,168 +80,149 @@ drc["lvs_rules"]=drclvs_home+"/calibreLVS.rul"
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drc["xrc_rules"]=drclvs_home+"/calibrexRC.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/freepdk45/layers.map"
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# minwidth_tx withcontact
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"]=0.09
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drc["minlength_channel"] = 0.05
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#well rules
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# WELL.1 Minimum spacing of nwell/pwell at different potential
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drc["pwell_to_nwell"] = 0.225
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# WELL.4 Minimum width of nwell/pwell
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drc["minwidth_well"] = 0.2
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#poly rules
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# POLY.1 Minimum width of poly
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drc["minwidth_poly"] = 0.05
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drc["minheight_poly"] = 0.0
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# POLY.2 Minimum spacing of poly AND active
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drc["poly_to_poly"] = 0.14
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# POLY.3 Minimum poly extension beyond active
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drc["poly_extend_active"] = 0.055
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# POLY.4 Minimum enclosure of active around gate
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drc["active_enclosure_gate"] = 0.07
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# POLY.5 Minimum spacing of field poly to active
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drc["poly_to_active"] = 0.05
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# POLY.6 Minimum Minimum spacing of field poly
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drc["poly_to_field_poly"] = 0.075
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# Not a rule
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drc["minarea_poly"] = 0.0
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#active
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drc["active_extend_gate"] = 0
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# ACTIVE.2 Minimum spacing of active
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drc["active_to_body_active"] = 0.08
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# ACTIVE.1 Minimum width of active
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drc["minwidth_active"] = 0.09
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drc["minheight_active"] = 0.09
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drc["minarea_active"] = 0
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# Not a rule
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drc["active_to_active"] = 0
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# ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
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drc["well_enclosure_active"] = 0.055
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 0.055
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# Not a rule
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drc["minarea_active"] = 0
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#Implant
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drc["implant_to_gate"] = 0.07
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# IMPLANT.1 Minimum spacing of nimplant/ pimplant to channel
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drc["implant_to_channel"] = 0.07
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# Not a rule
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drc["implant_enclose_active"] = 0
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# Not a rule
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drc["implant_enclose_contact"] = 0
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# IMPLANT.2 Minimum spacing of nimplant/ pimplant to contact
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drc["implant_to_contact"] = 0.025
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# IMPLANT.3 Minimum width/ spacing of nimplant/ pimplant
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drc["implant_to_implant"] = 0.045
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# IMPLANT.4 Minimum width/ spacing of nimplant/ pimplant
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drc["minwidth_implant"] = 0.045
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#Contact
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# CONTACT.1 Minimum width of contact
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drc["minwidth_contact"] = 0.065
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# CONTACT.2 Minimum spacing of contact
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drc["contact_to_contact"] = 0.075
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# CONTACT.4 Minimum enclosure of active around contact
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drc["active_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["active_extend_contact"] = 0.005
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# CONTACT.5 Minimum enclosure of poly around contact
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drc["poly_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.005
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drc["contact_to_poly"] = 0.0375 #changed from 0.035
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# CONTACT.6 Minimum spacing of contact and gate
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drc["contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["contact_to_poly"] = 0.090
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#Metal1
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# METAL1.1 Minimum width of metal1
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drc["minwidth_metal1"] = 0.065
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drc["minheight_metal1"] = 0.0
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# METAL1.2 Minimum spacing of metal1
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drc["metal1_to_metal1"] = 0.065
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# METAL1.3 Minimum enclosure around contact on two opposite sides
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drc["metal1_enclosure_contact"] = 0
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# Reserved for asymmetric enclosures
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drc["metal1_extend_contact"] = 0.035
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# METAL1.4 inimum enclosure around via1 on two opposite sides
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drc["metal1_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal1_enclosure_via1"] = 0
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# Not a rule
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drc["minarea_metal1"] = 0
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#via1
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# VIA1.1 Minimum width of via1
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drc["minwidth_via1"] = 0.065
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# VIA1.2 Minimum spacing of via1
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drc["via1_to_via1"] = 0.075
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#Metal2
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal2"] = 0.07
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drc["minheight_metal2"] = 0.0
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# METALINT.2 Minimum spacing of intermediate metal
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drc["metal2_to_metal2"] = 0.07
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal2_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal2_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0
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# Not a rule
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drc["minarea_metal2"] = 0
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#Via2
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via2"] = 0.065
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via2_to_via2"] = 0.075
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#Metal3
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal3"] = 0.07
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drc["minheight_metal3"] = 0.0
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# METALINT.2 Minimum spacing of intermediate metal
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drc["metal3_to_metal3"] = 0.07
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal3_extend_via2"] = 0.035
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drc["metal3_enclosure_via2"] = 0
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 0
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal3_extend_via3"]=0.035
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drc["metal3_enclosure_via3"] = 0
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via3"] = 0
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# Not a rule
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drc["minarea_metal3"] = 0
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#Via3
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via3"] = 0.065
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via3_to_via3"] = 0.07
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#Metal4
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# METALSMG.1 Minimum width of semi-global metal
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drc["minwidth_metal4"] = 0.14
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drc["minheight_metal4"] = 0.0
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drc["metal4_enclosure_via3"] = 0
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drc["metal4_extend_via3"] = 0.07
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# METALSMG.2 Minimum spacing of semi-global metal
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drc["metal4_to_metal4"] = 0.14
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# METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides
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drc["metal4_extend_via3"] = 0.07
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# Reserved for asymmetric enclosure
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drc["metal4_enclosure_via3"] = 0
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# METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides
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drc["metal4_enclosure_via4"] = 0
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# Reserved for asymmetric enclosure
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drc["metal4_extend_via4"] = 0.07
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drc["metal4_enclosure_via4"] = 0.07
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drc["minarea_metal4"] = 0
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#Via4
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drc["minwidth_via4"] = 0.14
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drc["via4_to_via4"] = 0.14
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# Metal 5-10 are ommitted
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#Metal5
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drc["minwidth_metal5"] = 0.14
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drc["minheight_metal5"] = 0.0
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drc["metal5_to_metal5"] = 0.14
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drc["metal5_extend_via4"] = 0.07
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drc["metal5_enclosure_via4"] = 0.07
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drc["minarea_metal5"] = 0
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#Via 5
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drc["minwidth_via5"] = 0.14
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drc["via5_to_via5"] = 0.14
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#Metal6
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drc["minwidth_metal6"] = 0.14
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drc["minheight_metal6"] = 0.0
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drc["metal6_to_metal6"] = 0.14
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drc["metal6_extend_via5"] = 0
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drc["metal6_enclosure_via5"] = 0
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#Via 6
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drc["minwidth_via6"] = 0.14
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drc["via6_to_via6"] = 0.14
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#Metal7
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drc["minwidth_metal7"] = 0.14
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drc["minheight_metal7"] = 0.0
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drc["metal7_to_metal7"] = 0.14
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drc["metal7_extend_via6"] = 0
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drc["metal7_enclosure_via6"] = 0
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#Via7
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drc["minwidth_via7"] = 0.14
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drc["via7_to_via7"] = 0.14
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#Metal8
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drc["minwidth_metal8"] = 0.14
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drc["minheight_metal8"] = 0.0
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drc["metal8_to_metal8"] = 0.14
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drc["metal8_extend_via7"] = 0
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drc["metal8_enclosure_via7"] = 0
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#Via8
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drc["minwidth_via8"] = 0.14
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drc["via8_to_via8"] = 0.14
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#Metal9
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drc["minwidth_metal9"] = 0.14
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drc["minheight_metal9"] = 0.0
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drc["metal9_to_metal9"] = 0.14
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drc["metal9_extend_via8"] = 0
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drc["metal9_enclosure_via8"] = 0
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#Via 9
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drc["minwidth_via9"] = 0.14
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drc["via9_to_via9"] = 0.14
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#Metal 10
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drc["minwidth_metal10"] = 0.14
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drc["minheight_metal10"] = 0.0
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drc["metal10_to_metal10"] = 0.14
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drc["metal10_extend_via9"] = 0
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drc["metal10_enclosure_via9"] = 0
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###################################################
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##END DRC/LVS Rules
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@ -67,102 +67,121 @@ drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
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# minwidth_tx withcontact
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drc["minwidth_tx"] = 1.2
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drc["minlength_channel"] = 0.6
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"] = 1.2
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drc["minlength_channel"] = 0.6
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#well rules
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drc["pwell_to_nwell"] = 0
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# 1.4 Minimum spacing between wells of different type (if both are drawn)
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drc["pwell_to_nwell"] = 0
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# 1.1 Minimum width
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drc["minwidth_well"] = 3.6
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#poly rules
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drc["minwidth_poly"] = 0.6
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drc["minheight_poly"] = 0.0
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drc["poly_to_poly"] = 0.9
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drc["poly_extend_active"] = 0.6
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drc["poly_to_polycontact"] = 1.2
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drc["active_enclosure_gate"] = 0.0
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drc["poly_to_active"] = 0.3
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# 3.1 Minimum width
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drc["minwidth_poly"] = 0.6
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# 3.2/3.2.a Minimum spacing over field/active
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drc["poly_to_poly"] = 0.9
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 0.6
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# ??
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drc["poly_to_polycontact"] = 1.2
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# ??
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drc["active_enclosure_gate"] = 0.0
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# 3.5 Minimum field poly to active
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drc["poly_to_active"] = 0.3
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# Not a rule
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drc["minarea_poly"] = 0.0
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#active
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drc["active_extend_gate"] = 0
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drc["active_to_body_active"] = 1.2 # Fix me
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drc["minwidth_active"] = 0.9
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drc["minheight_active"] = 0.9
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drc["minarea_active"] = 0.0
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drc["active_to_active"] = 0.9
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# ??
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drc["active_to_body_active"] = 1.2 # Fix me
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# 2.1 Minimum width
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drc["minwidth_active"] = 0.9
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# 2.2 Minimum spacing
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drc["active_to_active"] = 0.9
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# 2.3 Source/drain active to well edge
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drc["well_enclosure_active"] = 1.8
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 1.8
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# Not a rule
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drc["minarea_active"] = 0.0
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#Implant
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drc["implant_to_gate"] = 0
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drc["implant_to_channel"] = 0
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# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
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drc["implant_to_channel"] = 0.9
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# 4.2 Minimum select overlap of active
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drc["implant_enclose_active"] = 0.6
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# 4.3 Minimum select overlap of contact
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drc["implant_enclose_contact"] = 0.3
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# Not a rule
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drc["implant_to_contact"] = 0
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# Not a rule
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drc["implant_to_implant"] = 0
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# Not a rule
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drc["minwidth_implant"] = 0
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#Contact
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# 6.1 Exact contact size
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drc["minwidth_contact"] = 0.6
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drc["minwidth_active_contact"] = 0.6
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drc["minwidth_poly_contact"] = 0.6
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drc["active_enclosure_contact"] = 0.3
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drc["active_extend_contact"] = 0.3
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drc["poly_enclosure_contact"] = 0.3
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drc["poly_extend_contact"] = 0.3
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drc["contact_to_poly"] = 0.6
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# 5.3 Minimum contact spacing
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drc["contact_to_contact"] = 0.9
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drc["active_contact_to_active_contact"] = 0.9
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drc["poly_contact_to_poly_contact"] = 0.9
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# 6.2.b Minimum active overlap
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drc["active_enclosure_contact"] = 0.3
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# Reserved for asymmetric enclosure
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drc["active_extend_contact"] = 0.3
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# 5.2.b Minimum poly overlap
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drc["poly_enclosure_contact"] = 0.3
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.3
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# Reserved for other technologies
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drc["contact_to_gate"] = 0.6
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# 5.4 Minimum spacing to gate of transistor
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drc["contact_to_poly"] = 0.6
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drc["active_extend_active_contact"] = 0.3
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drc["poly_extend_poly_contact"] = 0.3
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drc["active_enclosure_active_contact"] = 0.3
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drc["poly_enclosure_poly_contact"] = 0.3
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#Metal1
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drc["minwidth_metal1"] = 0.9
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||||
drc["minheight_metal1"] = 0
|
||||
drc["metal1_to_metal1"] = 0.9
|
||||
drc["metal1_to_contact"] = 0.9
|
||||
drc["metal1_enclosure_contact"] = 0.3
|
||||
drc["metal1_extend_contact"] = 0.3
|
||||
drc["metal1_extend_via1"] = 0.3
|
||||
# 7.1 Minimum width
|
||||
drc["minwidth_metal1"] = 0.9
|
||||
# 7.2 Minimum spacing
|
||||
drc["metal1_to_metal1"] = 0.9
|
||||
# 7.3 Minimum overlap of any contact
|
||||
drc["metal1_enclosure_contact"] = 0.3
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal1_extend_contact"] = 0.3
|
||||
# 8.3 Minimum overlap by metal1
|
||||
drc["metal1_enclosure_via1"] = 0.3
|
||||
# Reserve for asymmetric enclosures
|
||||
drc["metal1_extend_via1"] = 0.3
|
||||
# Not a rule
|
||||
drc["minarea_metal1"] = 0
|
||||
drc["metal1_enclosure_active_contact"] = 0.3
|
||||
drc["metal1_enclosure_poly_contact"] = 0.3
|
||||
drc["metal1_extend_active_contact"] = 0.3
|
||||
drc["metal1_extend_poly_contact"] = 0.3
|
||||
|
||||
#via1
|
||||
drc["minwidth_via1"] = 0.6
|
||||
drc["via1_to_via1"] = 0.6
|
||||
drc["minselect_overlap_via1"] = 0.3 # Fix me
|
||||
# 8.1 Exact size
|
||||
drc["minwidth_via1"] = 0.6
|
||||
# 8.2 Minimum via1 spacing
|
||||
drc["via1_to_via1"] = 0.6
|
||||
|
||||
#Metal2
|
||||
drc["minwidth_metal2"] = 0.9
|
||||
drc["minheight_metal2"] = 0
|
||||
drc["metal2_to_metal2"] = 0.9
|
||||
drc["metal2_extend_via1"] = 0.3
|
||||
# 9.1 Minimum width
|
||||
drc["minwidth_metal2"] = 0.9
|
||||
# 9.2 Minimum spacing
|
||||
drc["metal2_to_metal2"] = 0.9
|
||||
# 9.3 Minimum overlap of via1
|
||||
drc["metal2_extend_via1"] = 0.3
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via1"] = 0.3
|
||||
# 14.3 Minimum overlap by metal2
|
||||
drc["metal2_extend_via2"] = 0.3
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via2"] = 0.3
|
||||
# Not a rule
|
||||
drc["minarea_metal2"] = 0
|
||||
|
||||
#Via2
|
||||
drc["minwidth_via2"] = 0.6
|
||||
# 14.2 Exact size
|
||||
drc["minwidth_via2"] = 0.6
|
||||
# 14.2 Minimum spacing
|
||||
drc["via2_to_via2"] = 0.9
|
||||
|
||||
#Metal3
|
||||
drc["minwidth_metal3"] = 1.5
|
||||
drc["minheight_metal3"] = 0.0
|
||||
drc["metal3_to_metal3"] = 0.9
|
||||
drc["metal3_extend_via2"] = 0.6
|
||||
drc["metal3_enclosure_via2"] = 0.6
|
||||
# 15.1 Minimum width
|
||||
drc["minwidth_metal3"] = 1.5
|
||||
# 15.2 Minimum spacing to metal3
|
||||
drc["metal3_to_metal3"] = 0.9
|
||||
# 15.3 Minimum overlap of via 2
|
||||
drc["metal3_extend_via2"] = 0.6
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via2"] = 0.6
|
||||
# Not a rule
|
||||
drc["minarea_metal3"] = 0
|
||||
|
||||
###################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue