mirror of https://github.com/VLSIDA/OpenRAM.git
Prune ptx code. Change sizes to be relative to min size.
This commit is contained in:
Matt Guthaus
parent
d4f8d63442
commit
1bcef7e3ee
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@ -470,7 +470,7 @@ class bank(design.design):
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"""
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# 4x Inverter
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self.inv4x = pinv(nmos_width=4*drc["minwidth_tx"])
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self.inv4x = pinv(4)
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self.add_mod(self.inv4x)
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self.nor2 = nor_2()
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@ -50,13 +50,13 @@ class control_logic(design.design):
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# Special gates: inverters for buffering
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self.inv = self.inv1 = pinv()
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self.add_mod(self.inv1)
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self.inv2 = pinv(nmos_width=2*drc["minwidth_tx"])
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self.inv2 = pinv(2)
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self.add_mod(self.inv2)
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self.inv4 = pinv(nmos_width=4*drc["minwidth_tx"])
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self.inv4 = pinv(4)
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self.add_mod(self.inv4)
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self.inv8 = pinv(nmos_width=8*drc["minwidth_tx"])
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self.inv8 = pinv(8)
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self.add_mod(self.inv8)
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self.inv16 = pinv(nmos_width=16*drc["minwidth_tx"])
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self.inv16 = pinv(16)
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self.add_mod(self.inv16)
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c = reload(__import__(OPTS.config.ms_flop_array))
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@ -21,16 +21,16 @@ class nand_2(design.design):
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unique_id = 1
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def __init__(self, nmos_width=2*drc["minwidth_tx"], height=bitcell.height):
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def __init__(self, size=2, height=bitcell.height):
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"""Constructor : Creates a cell for a simple 2 input nand"""
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name = "nand2_{0}".format(nand_2.unique_id)
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nand_2.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "create nand_2 structure {0} with size of {1}".format(name, nmos_width))
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self.nmos_size = nmos_width
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self.nmos_size = 2*size
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# FIXME why is this?
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self.pmos_size = nmos_width
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self.pmos_size = size
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self.tx_mults = 1
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self.height = height
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@ -21,16 +21,16 @@ class nand_3(design.design):
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unique_id = 1
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def __init__(self, nmos_width=3*drc["minwidth_tx"], height=bitcell.height):
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def __init__(self, size=1, height=bitcell.height):
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"""Constructor : Creates a cell for a simple 3 input nand"""
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name = "nand3_{0}".format(nand_3.unique_id)
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nand_3.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "create nand_3 structure {0} with size of {1}".format(name, nmos_width))
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self.nmos_size = nmos_width
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self.nmos_size = 3*size
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# FIXME: Why is this??
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self.pmos_size = 2 * nmos_width / 3
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self.pmos_size = 2*size
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self.tx_mults = 1
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self.height = height
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@ -20,7 +20,7 @@ class nor_2(design.design):
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unique_id = 1
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def __init__(self, nmos_width=drc["minwidth_tx"], height=bitcell.height):
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def __init__(self, size=1, height=bitcell.height):
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"""Constructor : Creates a cell for a simple 2 input nor"""
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name = "nor2_{0}".format(nor_2.unique_id)
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nor_2.unique_id += 1
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@ -29,7 +29,7 @@ class nor_2(design.design):
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debug.check(nmos_width==drc["minwidth_tx"], "Need to rewrite nor2 for sizing.")
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self.nmos_width = nmos_width
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self.nmos_size =
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self.height = height
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self.add_pins()
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@ -9,37 +9,47 @@ from globals import OPTS
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class pinv(design.design):
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"""
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This module generates gds of a parametrically sized inverter.
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This model use ptx to generate a inverter within a cetrain height.
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The inverter's cell_height should be the same as the 6t library cell.
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This module generates gds of a parametrically sized inverter. The
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size is specified as the nmos size (relative to minimum) and a
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beta value for choosing the pmos size. The inverter's cell_height
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is usually the same as the 6t library cell. The route_output will
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route the output to the right side of the cell for easier access.
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"""
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c = reload(__import__(OPTS.config.bitcell))
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bitcell = getattr(c, OPTS.config.bitcell)
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unique_id = 1
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def __init__(self, nmos_width=drc["minwidth_tx"], beta=parameter["pinv_beta"], height=bitcell.height, route_output=True):
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"""Constructor : Creates a cell for a simple inverter"""
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def __init__(self, size=1, beta=parameter["pinv_beta"], height=bitcell.height, route_output=True):
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# We need to keep unique names because outputting to GDSII
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# will use the last record with a given name. I.e., you will
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# over-write a design in GDS if one has and the other doesn't
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# have poly connected, for example.
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name = "pinv{0}".format(pinv.unique_id)
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pinv.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "create pinv structure {0} with size of {1}".format(name, nmos_width))
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debug.info(2, "create pinv structure {0} with size of {1}".format(name, size))
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self.nmos_width = nmos_width
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self.nmos_size = size
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self.pmos_size = beta*size
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self.beta = beta
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self.height = height
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self.route_output = route_output
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self.add_pins()
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self.create_layout()
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# for run-time, we won't check every transitor DRC/LVS independently
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# but this may be uncommented for debug purposes
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#self.DRC_LVS()
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def add_pins(self):
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"""Adds pins for spice netlist processing"""
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"""Adds pins for spice netlist"""
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self.add_pin_list(["A", "Z", "vdd", "gnd"])
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def create_layout(self):
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"""Calls all functions related to the generation of the layout(gds)"""
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"""Calls all functions related to the generation of the layout"""
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# These aren't for instantiating, but we use them to get the dimensions
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self.poly_contact = contact.contact(("poly", "contact", "metal1"))
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@ -66,45 +76,54 @@ class pinv(design.design):
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self.route_pins()
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def determine_tx_mults(self):
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"""Determines the number of fingers needed to achieve same size with a height constraint"""
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# check minimum distance between well
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minwidth_poly_contact = drc["minwidth_contact"] \
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+ 2 * drc["poly_enclosure_contact"]
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"""
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Determines the number of fingers needed to achieve the size within
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the height constraint. This may fail if the user has a tight height.
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"""
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# Do a quick sanity check and bail if unlikely feasible height
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# Sanity check. can we make an inverter in the height with minimum tx sizes?
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# Assume we need 3 metal 1 pitches (2 power rails, one between the tx for the drain)
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# plus the tx height
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nmos = ptx(tx_type="nmos")
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pmos = ptx(width=self.beta*drc["minwidth_tx"], tx_type="pmos")
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tx_height = nmos.height + pmos.height
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# rotated m1 pitch
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m1_pitch = self.poly_contact.width + drc["metal1_to_metal1"]
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metal_height = 4 * m1_pitch # This could be computed more accurately
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debug.check(self.height>tx_height + metal_height,"Cell height too small for our simple design rules.")
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# this should be 2*poly extension beyond active?
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minwidth_box_poly = 2 * drc["minwidth_poly"] \
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+ drc["poly_to_poly"]
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well_to_well = max(drc["pwell_to_nwell"],
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minwidth_poly_contact,
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minwidth_box_poly)
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# Determine the height left to the transistors to determine the number of fingers
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tx_height_available = self.height - metal_height
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# Divide the height according to beta
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nmos_height_available = 1.0/(self.beta+1) * tx_height_available
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pmos_height_available = tx_height_available - nmos_height_available
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# determine both mos enclosure sizes
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bot_mos_enclosure = 2 * (drc["well_enclosure_active"])
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top_mos_enclosure = 2 * max(drc["well_enclosure_active"],
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drc["metal1_to_metal1"] + 0.5 * drc["minwidth_metal1"])
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self.nmos_size = parameter["min_tx_size"]
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self.pmos_size = parameter["min_tx_size"] * self.beta
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# use multi finger if the cell is not big enough
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if self.nmos_size <= self.nmos_width:
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self.tx_mults = int(ceil(self.nmos_width / self.nmos_size))
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else:
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self.tx_mults = 1
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# Determine the number of mults for each to fit width into available space
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self.nmos_width = self.nmos_size*drc["minwidth_tx"]
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self.pmos_width = self.pmos_size*drc["minwidth_tx"]
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nmos_required_mults = max(int(ceil(self.nmos_width/nmos_height_available)),1)
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pmos_required_mults = max(int(ceil(self.pmos_width/pmos_height_available)),1)
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# The mults must be the same for easy connection of poly
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self.tx_mults = max(nmos_required_mults, pmos_required_mults)
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# Recompute each mult width and check it isn't too small
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# This could happen if the height is narrow and the size is small
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# User should pick a bigger size to fix it...
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self.nmos_width = self.nmos_width / self.tx_mults
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debug.check(self.nmos_width>=drc["minwidth_tx"],"Cannot finger NMOS transistors to fit cell height.")
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self.pmos_width = self.pmos_width / self.tx_mults
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debug.check(self.pmos_width>=drc["minwidth_tx"],"Cannot finger PMOS transistors to fit cell height.")
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def create_ptx(self):
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"""Intiializes a ptx object"""
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self.nmos = ptx(width=self.nmos_size,
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self.nmos = ptx(width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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connect_active=True,
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connect_poly=True)
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tx_type="nmos")
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self.add_mod(self.nmos)
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self.pmos = ptx(width=self.pmos_size,
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self.pmos = ptx(width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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connect_active=True,
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connect_poly=True)
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tx_type="pmos")
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self.add_mod(self.pmos)
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def setup_layout_constants(self):
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@ -40,17 +40,19 @@ class ptx(design.design):
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self.connect_poly = connect_poly
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self.num_contacts = num_contacts
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self.add_pins()
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self.create_spice()
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self.create_layout()
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# for run-time, we won't check every transitor DRC independently
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# but this may be uncommented for debug purposes
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#self.DRC()
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def add_pins(self):
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"""Adds pins for spice netlist"""
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self.add_pin_list(["D", "G", "S", "B"])
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def create_layout(self):
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"""Calls all functions related to the generation of the layout"""
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self.setup_layout_constants()
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self.add_active()
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self.add_well_implant()
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@ -58,6 +60,8 @@ class ptx(design.design):
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self.add_active_contacts()
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def create_spice(self):
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self.add_pins()
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self.spice.append("\n.SUBCKT {0} {1}".format(self.name,
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" ".join(self.pins)))
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self.spice.append("M{0} {1} {2} m={3} w={4}u l={5}u".format(self.tx_type,
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@ -75,7 +79,18 @@ class ptx(design.design):
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if self.num_contacts==None:
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self.num_contacts=self.calculate_num_contacts()
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# Determine layer types needed
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if self.tx_type == "nmos":
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self.implant_type = "n"
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self.well_type = "p"
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elif self.tx_type == "pmos":
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self.implant_type = "p"
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self.well_type = "n"
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else:
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self.error("Invalid transitor type.",-1)
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# This is not actually instantiated but used for calculations
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self.active_contact = contact(layer_stack=("active", "contact", "metal1"),
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dimensions=(1, self.num_contacts))
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@ -112,11 +127,19 @@ class ptx(design.design):
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self.poly_height = self.tx_width + 2*self.poly_extend_active
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# Well enclosure of active, ensure minwidth as well
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self.well_width = max(self.active_width + 2*drc["well_enclosure_active"],
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drc["minwidth_well"])
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self.well_height = max(self.tx_width + 2*drc["well_enclosure_active"],
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drc["minwidth_well"])
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if info["has_{}well".format(self.well_type)]:
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self.well_width = max(self.active_width + 2*drc["well_enclosure_active"],
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drc["minwidth_well"])
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self.well_height = max(self.tx_width + 2*drc["well_enclosure_active"],
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drc["minwidth_well"])
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self.height = self.well_height
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self.width = self.well_width
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else:
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# If no well, use the boundary of the active and poly
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self.height = self.poly_height
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self.width = self.active_width
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# The active offset is due to the well extension
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self.active_offset = vector([drc["well_enclosure_active"]]*2)
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@ -231,17 +254,8 @@ class ptx(design.design):
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"""
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Add an (optional) well and implant for the type of transistor.
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"""
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if self.tx_type == "nmos":
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implant_type = "n"
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well_type = "p"
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elif self.tx_type == "pmos":
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implant_type = "p"
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well_type = "n"
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else:
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self.error("Invalid transitor type.",-1)
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if info["has_{}well".format(well_type)]:
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self.add_rect(layer="{}well".format(well_type),
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if info["has_{}well".format(self.well_type)]:
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self.add_rect(layer="{}well".format(self.well_type),
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offset=(0,0),
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width=self.well_width,
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height=self.well_height)
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@ -249,7 +263,7 @@ class ptx(design.design):
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offset=(0,0),
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width=self.well_width,
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height=self.well_height)
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self.add_rect(layer="{}implant".format(implant_type),
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self.add_rect(layer="{}implant".format(self.implant_type),
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offset=self.active_offset,
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width=self.active_width,
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height=self.active_height)
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@ -25,18 +25,30 @@ class pinv_test(unittest.TestCase):
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import pinv
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import tech
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# debug.info(2, "Checking min size inverter")
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# tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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# self.local_check(tx)
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debug.info(2, "Checking min size inverter")
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tx = pinv.pinv(size=1, beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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debug.info(2, "Checking 2x min size inverter")
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tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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tx = pinv.pinv(size=2, beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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debug.info(2, "Checking 5x min size inverter")
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tx = pinv.pinv(nmos_width=5 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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tx = pinv.pinv(size=5, beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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debug.info(2, "Checking min size inverter with new beta")
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tx = pinv.pinv(size=1, beta=3)
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self.local_check(tx)
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debug.info(2, "Checking 2x size inverter with new beta")
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tx = pinv.pinv(size=2, beta=3)
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self.local_check(tx)
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debug.info(2, "Checking 5x size inverter with new beta")
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tx = pinv.pinv(size=4, beta=3)
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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