mirror of https://github.com/VLSIDA/OpenRAM.git
Move sense amp to tri gate routing to M3... not ideal.
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cd502895c4
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@ -106,8 +106,6 @@ class bank(design.design):
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self.route_bank_select()
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self.route_vdd_gnd()
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#self.route_vdd_supply()
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#self.route_gnd_supply()
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def add_modules(self):
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""" Add modules. The order should not matter! """
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@ -619,34 +617,14 @@ class bank(design.design):
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# Connection of data_out of sense amp to data_in
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tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).lc()
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sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).bc()
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self.add_path("metal2",[sa_data_out,tri_gate_in])
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# # if we need a bend or not
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# if tri_gate_in.x-sa_data_out.x>self.m2_pitch:
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# # We'll connect to the bottom of the SA pin
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# bendX = sa_data_out.x
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# else:
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# # We'll connect to the left of the SA pin
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# sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).lc()
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# bendX = tri_gate_in.x - 3*self.m3_width
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# bendY = tri_gate_in.y - 2*self.m2_width
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# # Connection point of M2 and M3 paths, below the tri gate and
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# # to the left of the tri gate input
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# bend = vector(bendX, bendY)
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# # Connect an M2 path to the gate
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# mid3 = [tri_gate_in.x, bendY] # guarantee down then left
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# self.add_path("metal2", [bend, mid3, tri_gate_in])
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# # connect up then right to sense amp
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# mid1 = vector(bendX,sa_data_out.y)
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# self.add_path("metal3", [bend, mid1, sa_data_out])
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# offset = bend - vector([0.5*drc["minwidth_metal3"]] * 2)
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# self.add_via(("metal2", "via2", "metal3"),offset)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=tri_gate_in,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=sa_data_out,
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rotate=90)
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self.add_path("metal3",[sa_data_out,tri_gate_in])
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def route_tri_gate_out(self):
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""" Metal 3 routing of tri_gate output data """
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Binary file not shown.
Binary file not shown.
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1524065602
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timestamp 1524499924
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<< nwell >>
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rect -2 45 38 73
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<< pwell >>
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@ -84,18 +84,8 @@ rect 15 46 19 50
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rect 25 34 29 38
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rect 24 19 28 23
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<< metal2 >>
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rect 13 46 15 50
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rect 15 34 25 38
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rect 15 9 19 34
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rect 19 5 20 9
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rect 15 0 19 5
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<< m3contact >>
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rect 15 5 19 9
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<< metal3 >>
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rect 14 9 20 10
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rect 14 5 15 9
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rect 19 5 20 9
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rect 14 4 20 5
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rect 15 0 19 34
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<< m3p >>
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rect 0 0 34 73
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<< labels >>
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1523920689
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timestamp 1524499497
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<< nwell >>
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rect -3 101 37 138
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rect -3 0 37 51
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@ -167,6 +167,7 @@ rect 32 181 33 185
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rect 13 169 16 177
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rect 13 165 15 169
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rect 4 148 8 163
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rect 12 157 15 161
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rect 12 156 16 157
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rect 12 148 16 152
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rect 4 132 8 144
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@ -197,7 +198,7 @@ rect 11 24 36 28
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<< m2contact >>
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rect 10 192 14 196
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rect 20 189 24 193
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rect 11 157 15 161
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rect 23 153 27 157
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rect 16 118 20 122
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rect 26 86 30 90
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rect 19 64 23 68
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@ -217,7 +218,7 @@ rlabel metal2 12 200 12 200 5 bl
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rlabel metal2 22 200 22 200 5 br
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rlabel m2contact 21 66 21 66 1 gnd
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rlabel m2contact 28 88 28 88 1 gnd
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rlabel m2contact 13 159 13 159 1 gnd
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rlabel m2contact 21 33 21 33 1 vdd
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rlabel m2contact 18 120 18 120 1 vdd
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rlabel m2contact 25 155 25 155 1 gnd
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<< end >>
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