mirror of https://github.com/VLSIDA/OpenRAM.git
Convert predecodes to use create_bus api
This commit is contained in:
Matt Guthaus
parent
ac22b1145f
commit
0175c88a16
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@ -50,52 +50,42 @@ class hierarchical_predecode(design.design):
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debug.error("Invalid number of predecode inputs.",-1)
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def setup_constraints(self):
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# The rail offsets are indexed by the label
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self.rails = {}
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# Non inverted input rails
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for rail_index in range(self.number_of_inputs):
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xoffset = rail_index * self.m2_pitch + 0.5*self.m2_width
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self.rails["in[{}]".format(rail_index)]=xoffset
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self.height = self.number_of_outputs * self.nand.height
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# x offset for input inverters
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self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
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# Creating the right hand side metal2 rails for output connections
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for rail_index in range(2 * self.number_of_inputs):
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xoffset = self.x_off_inv_1 + self.inv.width + ((rail_index+1) * self.m2_pitch) + 0.5*self.m2_width
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if rail_index < self.number_of_inputs:
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self.rails["Abar[{}]".format(rail_index)]=xoffset
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else:
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self.rails["A[{}]".format(rail_index-self.number_of_inputs)]=xoffset
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# x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (1 + 2*self.number_of_inputs) * self.m2_pitch
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch
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# x offset to output inverters
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self.x_off_inv_2 = self.x_off_nand + self.nand.width
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# Height width are computed
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self.width = self.x_off_inv_2 + self.inv.width
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self.height = self.number_of_outputs * self.nand.height
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def create_rails(self):
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""" Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """
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for label in self.rails.keys():
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# these are not primary inputs, so they shouldn't have a
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# label or LVS complains about different names on one net
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if label.startswith("in"):
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self.add_layout_pin(text=label,
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layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m1_width, self.m1_width),
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width=self.m2_width,
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height=self.height - 4*self.m1_width)
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else:
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self.add_rect(layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m1_width, 2*self.m1_width),
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width=self.m2_width,
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height=self.height - 4*self.m1_width)
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input_names = ["in[{}]".format(x) for x in range(self.number_of_inputs)]
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offset = vector(0.5*self.m2_width,self.m1_width)
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self.input_rails = self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=offset,
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names=input_names,
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length=self.height - 2*self.m1_width)
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invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
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decode_names = invert_names + non_invert_names
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offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, self.m1_width)
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self.decode_rails = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=offset,
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names=decode_names,
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length=self.height - 2*self.m1_width)
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def add_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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@ -176,14 +166,14 @@ class hierarchical_predecode(design.design):
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y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1m2.width + self.m1_space
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in_pin = "in[{}]".format(num)
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a_pin = "A[{}]".format(num)
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in_pos = vector(self.rails[in_pin],y_offset)
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a_pos = vector(self.rails[a_pin],y_offset)
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in_pos = vector(self.input_rails[in_pin].x,y_offset)
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a_pos = vector(self.decode_rails[a_pin].x,y_offset)
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self.add_path("metal1",[in_pos, a_pos])
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=[self.rails[in_pin], y_offset],
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offset=[self.input_rails[in_pin].x, y_offset],
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rotate=90)
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=[self.rails[a_pin], y_offset],
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offset=[self.decode_rails[a_pin].x, y_offset],
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rotate=90)
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def route_output_inverters(self):
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@ -222,7 +212,7 @@ class hierarchical_predecode(design.design):
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y_offset = (inv_num+1) * self.inv.height - 3*self.m1_space
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inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc()
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0)
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rail_pos = vector(self.rails[out_pin],y_offset)
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rail_pos = vector(self.decode_rails[out_pin].x,y_offset)
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self.add_path("metal1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=rail_pos,
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@ -231,7 +221,7 @@ class hierarchical_predecode(design.design):
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#route input
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inv_in_pos = self.in_inst[inv_num].get_pin("A").lc()
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in_pos = vector(self.rails[in_pin],inv_in_pos.y)
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in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y)
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self.add_path("metal1", [in_pos, inv_in_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=in_pos,
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@ -253,7 +243,7 @@ class hierarchical_predecode(design.design):
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# this will connect pins A,B or A,B,C
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for rail_pin,gate_pin in zip(index_lst,gate_lst):
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pin_pos = self.nand_inst[k].get_pin(gate_pin).lc()
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rail_pos = vector(self.rails[rail_pin], pin_pos.y)
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rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y)
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self.add_path("metal1", [rail_pos, pin_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=rail_pos,
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