Added netlist only configuration option.

compiler/globals.py

@@ -204,6 +204,11 @@ def read_config(config_file, is_unit_test=True):
 
     OPTS.is_unit_test=is_unit_test
 
+    # If we are only generating a netlist, we can't do DRC/LVS
+    if OPTS.netlist_only:
+        OPTS.check_lvsdrc=False
+    
+
     # If config didn't set output name, make a reasonable default.
     if (OPTS.output_name == ""):
         OPTS.output_name = "sram_{0}rw_{1}b_{2}w_{3}bank_{4}".format(OPTS.rw_ports,
@@ -372,6 +377,9 @@ def report_status():
     print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
                                                           OPTS.num_words,
                                                           OPTS.num_banks))
+    if OPTS.netlist_only:
+        print("Netlist only mode (no physical design is being done).")
+    
     if not OPTS.check_lvsdrc:
         print("DRC/LVS/PEX checking is disabled.")
     

compiler/openram.py

@@ -40,7 +40,10 @@ report_status()
 import verify
 import sram
 
-output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in ["sp","gds","v","lib","lef"]]
+output_extensions = ["sp","v","lib"]
+if not OPTS.netlist_only:
+    output_extensions.extend(["gds","lef"])
+output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]
 print("Output files are: ")
 print(*output_files,sep="\n")
 

compiler/options.py

@@ -18,6 +18,8 @@ class options(optparse.Values):
     # This is the verbosity level to control debug information. 0 is none, 1
     # is minimal, etc.
     debug_level = 0
+    # When enabled, layout is not generated (and no DRC or LVS are performed)
+    netlist_only = False
     # This determines whether  LVS and DRC is checked for each submodule.
     check_lvsdrc = True
     # Variable to select the variant of spice

compiler/sram.py

@@ -99,19 +99,20 @@ class sram():
         lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
         print_time("Characterization", datetime.datetime.now(), start_time)
 
-        # Write the layout
-        start_time = datetime.datetime.now()
-        gdsname = OPTS.output_path + self.s.name + ".gds"
-        print("GDS: Writing to {0}".format(gdsname))
-        self.s.gds_write(gdsname)
-        print_time("GDS", datetime.datetime.now(), start_time)
+        if not OPTS.netlist_only:
+            # Write the layout
+            start_time = datetime.datetime.now()
+            gdsname = OPTS.output_path + self.s.name + ".gds"
+            print("GDS: Writing to {0}".format(gdsname))
+            self.s.gds_write(gdsname)
+            print_time("GDS", datetime.datetime.now(), start_time)
 
-        # Create a LEF physical model
-        start_time = datetime.datetime.now()
-        lefname = OPTS.output_path + self.s.name + ".lef"
-        print("LEF: Writing to {0}".format(lefname))
-        self.s.lef_write(lefname)
-        print_time("LEF", datetime.datetime.now(), start_time)
+            # Create a LEF physical model
+            start_time = datetime.datetime.now()
+            lefname = OPTS.output_path + self.s.name + ".lef"
+            print("LEF: Writing to {0}".format(lefname))
+            self.s.lef_write(lefname)
+            print_time("LEF", datetime.datetime.now(), start_time)
 
         # Write a verilog model
         start_time = datetime.datetime.now()