mirror of https://github.com/VLSIDA/OpenRAM.git
Fix spacing between adjacent decoders
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ffc866ef78
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6133d54684
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@ -68,7 +68,7 @@ class hierarchical_predecode(design.design):
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def create_rails(self):
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""" Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """
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input_names = ["in[{}]".format(x) for x in range(self.number_of_inputs)]
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offset = vector(0.5*self.m2_width,self.m1_width)
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offset = vector(0.5*self.m2_width,2*self.m1_width)
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self.input_rails = self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=offset,
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@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
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invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
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decode_names = invert_names + non_invert_names
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offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, self.m1_width)
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offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width)
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self.decode_rails = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=offset,
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