mirror of https://github.com/VLSIDA/OpenRAM.git
Limit sizes for dff_buf too. Add comments about restriction.
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@ -20,6 +20,12 @@ class dff_buf(design.design):
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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# This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
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# This causes a DRC in the pinv which assumes min width rails. This ensures the output
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# contact does not violate spacing to the rail in the NMOS.
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debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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from importlib import reload
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c = reload(__import__(OPTS.dff))
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self.mod_dff = getattr(c, OPTS.dff)
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@ -19,13 +19,16 @@ class dff_inv(design.design):
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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# This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
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# This causes a DRC in the pinv which assumes min width rails. This ensures the output
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# contact does not violate spacing to the rail in the NMOS.
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debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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from importlib import reload
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c = reload(__import__(OPTS.dff))
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self.mod_dff = getattr(c, OPTS.dff)
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self.dff = self.mod_dff("dff")
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self.add_mod(self.dff)
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debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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self.inv1 = pinv(size=inv_size,height=self.dff.height)
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self.add_mod(self.inv1)
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