mirror of https://github.com/VLSIDA/OpenRAM.git
Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.
This commit is contained in:
Michael Timothy Grimes
commit
e4a94e8597
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@ -166,7 +166,6 @@ class delay():
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self.sf.write("\n* Generation of control signals\n")
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self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage)
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self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage)
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self.stim.gen_constant(sig_name="OEb", v_val=self.vdd_voltage)
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self.sf.write("\n* Generation of global clock signal\n")
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self.stim.gen_constant(sig_name="CLK", v_val=0)
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@ -621,7 +620,6 @@ class delay():
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.web_values.append(1)
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self.oeb_values.append(1)
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self.csb_values.append(1)
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self.add_data(data)
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@ -637,7 +635,6 @@ class delay():
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self.t_current += self.period
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self.web_values.append(1)
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self.oeb_values.append(0)
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self.csb_values.append(0)
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self.add_data(data)
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@ -654,7 +651,6 @@ class delay():
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self.t_current += self.period
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self.web_values.append(0)
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self.oeb_values.append(1)
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self.csb_values.append(0)
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self.add_data(data)
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@ -674,7 +670,6 @@ class delay():
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# Control logic signals each cycle
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self.web_values = []
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self.oeb_values = []
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self.csb_values = []
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# Address and data values for each address/data bit
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@ -798,4 +793,3 @@ class delay():
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""" Generates the control signals """
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self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05)
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self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05)
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self.stim.gen_pwl("oeb", self.cycle_times, self.oeb_values, self.period, self.slew, 0.05)
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@ -22,9 +22,9 @@ class bank(design.design):
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def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
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mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver",
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mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
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"bitcell_array", "sense_amp_array", "precharge_array",
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"column_mux_array", "write_driver_array", "tri_gate_array",
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"column_mux_array", "write_driver_array",
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"dff", "bank_select"]
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from importlib import reload
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for mod_name in mod_list:
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@ -95,8 +95,7 @@ class bank(design.design):
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self.add_pin("s_en{0}".format(k), "INPUT")
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for k in range(self.total_write):
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self.add_pin("w_en{0}".format(k), "INPUT")
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for pin in ["tri_en_bar","tri_en",
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"clk_buf_bar","clk_buf"]:
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for pin in ["clk_buf_bar","clk_buf"]:
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self.add_pin(pin,"INPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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@ -107,15 +106,12 @@ class bank(design.design):
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self.route_precharge_to_bitcell_array()
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self.route_col_mux_to_bitcell_array()
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self.route_sense_amp_to_col_mux_or_bitcell_array()
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#self.route_sense_amp_to_trigate()
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#self.route_tri_gate_out()
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self.route_sense_amp_out()
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self.route_wordline_driver()
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self.route_write_driver()
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self.route_row_decoder()
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self.route_column_address_lines()
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self.route_control_lines()
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self.add_control_pins()
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if self.num_banks > 1:
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self.route_bank_select()
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@ -132,8 +128,6 @@ class bank(design.design):
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self.add_column_mux_array()
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self.add_sense_amp_array()
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self.add_write_driver_array()
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# Not needed for single bank
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#self.add_tri_gate_array()
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# To the left of the bitcell array
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self.add_row_decoder()
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@ -161,9 +155,10 @@ class bank(design.design):
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self.supply_rail_pitch = self.supply_rail_width + 4*self.m2_space
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# Number of control lines in the bus
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self.num_control_lines = 6
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self.num_control_lines = 4
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# The order of the control signals on the control bus:
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self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en0", "s_en0"]
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self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
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# These will be outputs of the gaters if this is multibank, if not, normal signals.
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if self.num_banks > 1:
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self.control_signals = ["gated_"+str for str in self.input_control_signals]
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@ -186,7 +181,6 @@ class bank(design.design):
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def create_modules(self):
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""" Create all the modules using the class loader """
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self.tri = self.mod_tri_gate()
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self.bitcell = self.mod_bitcell()
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self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols,
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@ -227,10 +221,6 @@ class bank(design.design):
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self.row_decoder = self.mod_decoder(rows=self.num_rows)
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self.add_mod(self.row_decoder)
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self.tri_gate_array = self.mod_tri_gate_array(columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.tri_gate_array)
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self.wordline_driver = self.mod_wordline_driver(rows=self.num_rows)
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self.add_mod(self.wordline_driver)
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@ -358,21 +348,6 @@ class bank(design.design):
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temp.extend([self.prefix+"w_en{0}".format(k), "vdd", "gnd"])
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self.connect_inst(temp)
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def add_tri_gate_array(self):
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""" data tri gate to drive the data bus """
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y_offset = self.sense_amp_array.height+self.column_mux_height \
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+ self.m2_gap + self.tri_gate_array.height
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self.tri_gate_array_inst=self.add_inst(name="tri_gate_array",
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mod=self.tri_gate_array,
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offset=vector(0,y_offset).scale(-1,-1))
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temp = []
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for i in range(self.word_size):
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temp.append("sa_out[{0}]".format(i))
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for i in range(self.word_size):
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temp.append("dout0[{0}]".format(i))
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temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"])
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self.connect_inst(temp)
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def add_row_decoder(self):
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""" Add the hierarchical row decoder """
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@ -498,7 +473,6 @@ class bank(design.design):
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self.precharge_array_inst[0],
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self.sense_amp_array_inst[0],
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self.write_driver_array_inst[0],
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# self.tri_gate_array_inst,
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self.row_decoder_inst[0],
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self.wordline_driver_inst[0]]
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# Add these if we use the part...
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@ -544,12 +518,10 @@ class bank(design.design):
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control bus, power ring, etc. """
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#The minimum point is either the bottom of the address flops,
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#the column decoder (if there is one) or the tristate output
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#driver.
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# Leave room for the output below the tri gate.
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#tri_gate_min_y_offset = self.tri_gate_array_inst.by() - 3*self.m2_pitch
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#the column decoder (if there is one).
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write_driver_min_y_offset = self.write_driver_array_inst[0].by() - 3*self.m2_pitch
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row_decoder_min_y_offset = self.row_decoder_inst[0].by()
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if self.col_addr_size > 0:
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col_decoder_min_y_offset = self.col_decoder_inst[0].by()
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else:
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@ -557,10 +529,10 @@ class bank(design.design):
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if self.num_banks>1:
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# The control gating logic is below the decoder
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# Min of the control gating logic and tri gate.
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# Min of the control gating logic and write driver.
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self.min_y_offset = min(col_decoder_min_y_offset - self.bank_select.height, write_driver_min_y_offset)
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else:
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# Just the min of the decoder logic logic and tri gate.
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# Just the min of the decoder logic logic and write driver.
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self.min_y_offset = min(col_decoder_min_y_offset, write_driver_min_y_offset)
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# The max point is always the top of the precharge bitlines
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@ -586,13 +558,15 @@ class bank(design.design):
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# and control lines.
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# The bank is at (0,0), so this is to the left of the y-axis.
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# 2 pitches on the right for vias/jogs to access the inputs
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control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, 0)
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control_bus_length = self.bitcell_array_inst.uy()
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self.bus_xoffset = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=control_bus_offset,
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names=self.control_signals,
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length=control_bus_length)
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control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset)
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control_bus_length = self.max_y_offset - self.min_y_offset
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self.bus_xoffset = self.create_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=control_bus_offset,
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names=self.control_signals,
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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@ -657,20 +631,7 @@ class bank(design.design):
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self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
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vector(connect_br.x,yoffset), connect_br])
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def route_sense_amp_to_trigate(self):
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""" Routing of sense amp output to tri_gate input """
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for i in range(self.word_size):
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# Connection of data_out of sense amp to data_in
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tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).lc()
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sa_data_out = self.sense_amp_array_inst[0].get_pin("data[{}]".format(i)).bc()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=tri_gate_in)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=sa_data_out)
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self.add_path("metal3",[sa_data_out,tri_gate_in])
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def route_sense_amp_out(self):
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""" Add pins for the sense amp output """
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for i in range(self.word_size):
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@ -681,16 +642,6 @@ class bank(design.design):
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height=data_pin.height(),
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width=data_pin.width()),
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def route_tri_gate_out(self):
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""" Metal 3 routing of tri_gate output data """
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for i in range(self.word_size):
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data_pin = self.tri_gate_array_inst.get_pin("out[{}]".format(i))
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self.add_layout_pin_rect_center(text="dout0[{}]".format(i),
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layer=data_pin.layer,
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width()),
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def route_row_decoder(self):
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""" Routes the row decoder inputs and supplies """
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@ -837,8 +788,6 @@ class bank(design.design):
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# Connection from the central bus to the main control block crosses
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# pre-decoder and this connection is in metal3
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connection = []
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#connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc()))
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#connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc()))
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connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst[0].get_pin("en").lc()))
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connection.append((self.prefix+"w_en0", self.write_driver_array_inst[0].get_pin("en").lc()))
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connection.append((self.prefix+"s_en0", self.sense_amp_array_inst[0].get_pin("en").lc()))
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@ -862,52 +811,7 @@ class bank(design.design):
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offset=control_via_pos,
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rotate=90)
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def add_control_pins(self):
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""" Add the control signal input pins """
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for ctrl in self.control_signals:
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# xoffsets are the center of the rail
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x_offset = self.bus_xoffset[ctrl].x - 0.5*self.m2_width
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if self.num_banks > 1:
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# it's not an input pin if we have multiple banks
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self.add_label_pin(text=ctrl,
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layer="metal2",
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offset=vector(x_offset, self.min_y_offset),
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width=self.m2_width,
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height=self.max_y_offset-self.min_y_offset)
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else:
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self.add_layout_pin(text=ctrl,
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layer="metal2",
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offset=vector(x_offset, self.min_y_offset),
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width=self.m2_width,
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height=self.max_y_offset-self.min_y_offset)
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def connect_rail_from_right(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pin = inst.get_pin(pin).lc()
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rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y)
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self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
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# Bring it up to M2 for M2/M3 routing
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self.add_via(layers=("metal1","via1","metal2"),
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offset=in_pin + contact.m1m2.offset,
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rotate=90)
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self.add_via(layers=("metal2","via2","metal3"),
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offset=in_pin + self.m2m3_via_offset,
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rotate=90)
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def connect_rail_from_left(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pin = inst.get_pin(pin).rc()
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rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y)
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self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
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self.add_via(layers=("metal1","via1","metal2"),
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offset=in_pin + contact.m1m2.offset,
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rotate=90)
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self.add_via(layers=("metal2","via2","metal3"),
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offset=in_pin + self.m2m3_via_offset,
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rotate=90)
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def analytical_delay(self, slew, load):
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""" return analytical delay of the bank"""
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@ -921,8 +825,6 @@ class bank(design.design):
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self.bitcell_array.output_load())
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# output load of bitcell_array is set to be only small part of bl for sense amp.
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data_t_DATA_delay = self.tri_gate_array.analytical_delay(bl_t_data_out_delay.slew, load)
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result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
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result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay
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return result
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@ -19,9 +19,9 @@ class bank_select(design.design):
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design.design.__init__(self, name)
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# Number of control lines in the bus
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self.num_control_lines = 6
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self.num_control_lines = 4
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# The order of the control signals on the control bus:
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self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
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self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
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# These will be outputs of the gaters if this is multibank
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self.control_signals = ["gated_"+str for str in self.input_control_signals]
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@ -96,7 +96,7 @@ class bank_select(design.design):
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# These require OR (nor2+inv) gates since they are active low.
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# (writes occur on clk low)
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if input_name in ("clk_buf", "tri_en_bar"):
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if input_name in ("clk_buf"):
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self.logic_inst.append(self.add_inst(name=name_nor,
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mod=self.nor2,
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@ -161,7 +161,7 @@ class bank_select(design.design):
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self.add_label_pin(text="bank_sel_bar",
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layer="metal2",
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offset=vector(xoffset_bank_sel_bar, 0),
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height=2*self.inv.height)
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height=self.inv.height)
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=bank_sel_bar_pin.rc())
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@ -173,7 +173,7 @@ class bank_select(design.design):
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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if input_name in ("clk_buf", "tri_en_bar"):
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if input_name in ("clk_buf"):
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xoffset_bank_signal = xoffset_bank_sel_bar
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else:
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xoffset_bank_signal = xoffset_bank_sel
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@ -52,7 +52,7 @@ class control_logic(design.design):
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dff = dff_inv()
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dff_height = dff.height
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self.ctrl_dff_array = dff_inv_array(rows=3,columns=1)
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self.ctrl_dff_array = dff_inv_array(rows=2,columns=1)
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self.add_mod(self.ctrl_dff_array)
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self.nand2 = pnand2(height=dff_height)
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@ -93,16 +93,14 @@ class control_logic(design.design):
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#self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"])
|
||||
|
||||
# List of input control signals
|
||||
self.input_list =["csb","web","oeb"]
|
||||
self.dff_output_list =["cs_bar", "cs", "we_bar", "we", "oe_bar", "oe"]
|
||||
self.input_list =["csb","web"]
|
||||
self.dff_output_list =["cs_bar", "cs", "we_bar", "we"]
|
||||
# list of output control signals (for making a vertical bus)
|
||||
self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs", "oe"]
|
||||
self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"]
|
||||
# leave space for the bus plus one extra space
|
||||
self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
|
||||
# Ooutputs to the bank
|
||||
# Outputs to the bank
|
||||
self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
|
||||
# # with tri/tri_en
|
||||
# self.output_list = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_buf_bar", "clk_buf"]
|
||||
self.supply_list = ["vdd", "gnd"]
|
||||
|
||||
|
||||
|
|
@ -139,10 +137,11 @@ class control_logic(design.design):
|
|||
# This offset is used for placement of the control logic in
|
||||
# the SRAM level.
|
||||
self.control_logic_center = vector(self.ctrl_dff_inst.rx(), self.rbl_inst.by())
|
||||
|
||||
self.height = self.rbl_inst.uy()
|
||||
|
||||
# Extra pitch on top and right
|
||||
self.height = self.rbl_inst.uy() + self.m3_pitch
|
||||
# Max of modules or logic rows
|
||||
self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst]))
|
||||
self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch
|
||||
|
||||
|
||||
def add_routing(self):
|
||||
|
|
@ -190,14 +189,14 @@ class control_logic(design.design):
|
|||
(y_off,mirror)=self.get_offset(row)
|
||||
|
||||
|
||||
# input: OE, clk_buf_bar,CS output: rbl_in_bar
|
||||
# input: clk_buf_bar,CS output: rbl_in_bar
|
||||
self.rbl_in_bar_offset = vector(x_off, y_off)
|
||||
self.rbl_in_bar_inst=self.add_inst(name="nand3_rbl_in_bar",
|
||||
mod=self.nand3,
|
||||
mod=self.nand2,
|
||||
offset=self.rbl_in_bar_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["clk_buf_bar", "oe", "cs", "rbl_in_bar", "vdd", "gnd"])
|
||||
x_off += self.nand3.width
|
||||
self.connect_inst(["clk_buf_bar", "cs", "rbl_in_bar", "vdd", "gnd"])
|
||||
x_off += self.nand2.width
|
||||
|
||||
# input: rbl_in_bar, output: rbl_in
|
||||
self.rbl_in_offset = vector(x_off, y_off)
|
||||
|
|
@ -237,76 +236,11 @@ class control_logic(design.design):
|
|||
|
||||
self.row_end_inst.append(self.s_en_inst)
|
||||
|
||||
def add_trien_row(self, row):
|
||||
x_off = self.ctrl_dff_array.width + self.internal_bus_width
|
||||
(y_off,mirror)=self.get_offset(row)
|
||||
|
||||
|
||||
x_off += self.nand2.width
|
||||
|
||||
# BUFFER INVERTERS FOR TRI_EN
|
||||
tri_en_offset = vector(x_off, y_off)
|
||||
self.tri_en_inst=self.add_inst(name="inv_tri_en1",
|
||||
mod=self.inv2,
|
||||
offset=tri_en_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["pre_tri_en_bar", "pre_tri_en1", "vdd", "gnd"])
|
||||
x_off += self.inv2.width
|
||||
|
||||
tri_en_buf1_offset = vector(x_off, y_off)
|
||||
self.tri_en_buf1_inst=self.add_inst(name="tri_en_buf1",
|
||||
mod=self.inv2,
|
||||
offset=tri_en_buf1_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["pre_tri_en1", "pre_tri_en_bar1", "vdd", "gnd"])
|
||||
x_off += self.inv2.width
|
||||
|
||||
tri_en_buf2_offset = vector(x_off, y_off)
|
||||
self.tri_en_buf2_inst=self.add_inst(name="tri_en_buf2",
|
||||
mod=self.inv8,
|
||||
offset=tri_en_buf2_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["pre_tri_en_bar1", "tri_en", "vdd", "gnd"])
|
||||
|
||||
self.row_end_inst.append(self.tri_en_inst)
|
||||
|
||||
def add_trien_bar_row(self, row):
|
||||
x_off = self.ctrl_dff_array.width + self.internal_bus_width
|
||||
(y_off,mirror)=self.get_offset(row)
|
||||
|
||||
|
||||
# input: OE, clk_buf_bar output: tri_en_bar
|
||||
tri_en_bar_offset = vector(x_off,y_off)
|
||||
self.tri_en_bar_inst=self.add_inst(name="nand2_tri_en",
|
||||
mod=self.nand2,
|
||||
offset=tri_en_bar_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["clk_buf_bar", "oe", "pre_tri_en_bar", "vdd", "gnd"])
|
||||
x_off += self.nand2.width
|
||||
|
||||
# BUFFER INVERTERS FOR TRI_EN
|
||||
tri_en_bar_buf1_offset = vector(x_off, y_off)
|
||||
self.tri_en_bar_buf1_inst=self.add_inst(name="tri_en_bar_buf1",
|
||||
mod=self.inv2,
|
||||
offset=tri_en_bar_buf1_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["pre_tri_en_bar", "pre_tri_en2", "vdd", "gnd"])
|
||||
x_off += self.inv2.width
|
||||
|
||||
tri_en_bar_buf2_offset = vector(x_off, y_off)
|
||||
self.tri_en_bar_buf2_inst=self.add_inst(name="tri_en_bar_buf2",
|
||||
mod=self.inv8,
|
||||
offset=tri_en_bar_buf2_offset,
|
||||
mirror=mirror)
|
||||
self.connect_inst(["pre_tri_en2", "tri_en_bar", "vdd", "gnd"])
|
||||
x_off += self.inv8.width
|
||||
|
||||
self.row_end_inst.append(self.tri_en_bar_buf2_inst)
|
||||
|
||||
def route_dffs(self):
|
||||
""" Route the input inverters """
|
||||
|
||||
dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we", "oe"])
|
||||
dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we"])
|
||||
self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets)
|
||||
|
||||
# Connect the clock rail to the other clock rail
|
||||
|
|
@ -320,7 +254,6 @@ class control_logic(design.design):
|
|||
|
||||
self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb")
|
||||
self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web")
|
||||
self.copy_layout_pin(self.ctrl_dff_inst, "din[2]", "oeb")
|
||||
|
||||
|
||||
def add_dffs(self):
|
||||
|
|
@ -388,7 +321,7 @@ class control_logic(design.design):
|
|||
|
||||
def route_rbl_in(self):
|
||||
""" Connect the logic for the rbl_in generation """
|
||||
rbl_in_map = zip(["A", "B", "C"], ["clk_buf_bar", "oe", "cs"])
|
||||
rbl_in_map = zip(["A", "B"], ["clk_buf_bar", "cs"])
|
||||
self.connect_vertical_bus(rbl_in_map, self.rbl_in_bar_inst, self.rail_offsets)
|
||||
|
||||
# Connect the NAND3 output to the inverter
|
||||
|
|
@ -475,44 +408,6 @@ class control_logic(design.design):
|
|||
|
||||
self.connect_output(self.w_en_inst, "Z", "w_en")
|
||||
|
||||
def route_trien(self):
|
||||
|
||||
# Connect the NAND2 output to the buffer
|
||||
tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center()
|
||||
inv_in_pos = self.tri_en_inst.get_pin("A").center()
|
||||
mid1 = vector(tri_en_bar_pos.x,inv_in_pos.y)
|
||||
self.add_wire(("metal1","via1","metal2"),[tri_en_bar_pos,mid1,inv_in_pos])
|
||||
|
||||
# Connect the INV output to the buffer
|
||||
tri_en_pos = self.tri_en_inst.get_pin("Z").center()
|
||||
inv_in_pos = self.tri_en_buf1_inst.get_pin("A").center()
|
||||
mid_xoffset = 0.5*(tri_en_pos.x + inv_in_pos.x)
|
||||
mid1 = vector(mid_xoffset,tri_en_pos.y)
|
||||
mid2 = vector(mid_xoffset,inv_in_pos.y)
|
||||
self.add_path("metal1",[tri_en_pos,mid1,mid2,inv_in_pos])
|
||||
|
||||
self.add_path("metal1",[self.tri_en_buf1_ist.get_pin("Z").center(), self.tri_en_buf2_inst.get_pin("A").center()])
|
||||
|
||||
self.connect_output(self.tri_en_buf2_inst, "Z", "tri_en")
|
||||
|
||||
def route_trien_bar(self):
|
||||
|
||||
trien_map = zip(["A", "B"], ["clk_buf_bar", "oe"])
|
||||
self.connect_vertical_bus(trien_map, self.tri_en_bar_inst, self.rail_offsets)
|
||||
|
||||
# Connect the NAND2 output to the buffer
|
||||
tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center()
|
||||
inv_in_pos = self.tri_en_bar_buf1_inst.get_pin("A").center()
|
||||
mid_xoffset = 0.5*(tri_en_bar_pos.x + inv_in_pos.x)
|
||||
mid1 = vector(mid_xoffset,tri_en_bar_pos.y)
|
||||
mid2 = vector(mid_xoffset,inv_in_pos.y)
|
||||
self.add_path("metal1",[tri_en_bar_pos,mid1,mid2,inv_in_pos])
|
||||
|
||||
self.add_path("metal1",[self.tri_en_bar_buf1_inst.get_pin("Z").center(), self.tri_en_bar_buf2_inst.get_pin("A").center()])
|
||||
|
||||
self.connect_output(self.tri_en_bar_buf2_inst, "Z", "tri_en_bar")
|
||||
|
||||
|
||||
def route_sen(self):
|
||||
rbl_out_pos = self.rbl_inst.get_pin("out").bc()
|
||||
in_pos = self.pre_s_en_bar_inst.get_pin("A").lc()
|
||||
|
|
|
|||
|
|
@ -125,28 +125,21 @@ class dff_array(design.design):
|
|||
# Create vertical spines to a single horizontal rail
|
||||
clk_pin = self.dff_insts[0,0].get_pin("clk")
|
||||
debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2")
|
||||
if self.columns==1:
|
||||
self.add_layout_pin(text="clk",
|
||||
layer="metal2",
|
||||
offset=clk_pin.ll().scale(1,0),
|
||||
width=self.m2_width,
|
||||
height=self.height)
|
||||
else:
|
||||
self.add_layout_pin_segment_center(text="clk",
|
||||
layer="metal3",
|
||||
start=vector(0,self.m3_pitch+self.m3_width),
|
||||
end=vector(self.width,self.m3_pitch+self.m3_width))
|
||||
for col in range(self.columns):
|
||||
clk_pin = self.dff_insts[0,col].get_pin("clk")
|
||||
# Make a vertical strip for each column
|
||||
self.add_rect(layer="metal2",
|
||||
offset=clk_pin.ll().scale(1,0),
|
||||
width=self.m2_width,
|
||||
height=self.height)
|
||||
# Drop a via to the M3 pin
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=vector(clk_pin.cx(),self.m3_pitch+self.m3_width))
|
||||
|
||||
self.add_layout_pin_segment_center(text="clk",
|
||||
layer="metal3",
|
||||
start=vector(0,self.m3_pitch+self.m3_width),
|
||||
end=vector(self.width,self.m3_pitch+self.m3_width))
|
||||
for col in range(self.columns):
|
||||
clk_pin = self.dff_insts[0,col].get_pin("clk")
|
||||
# Make a vertical strip for each column
|
||||
self.add_rect(layer="metal2",
|
||||
offset=clk_pin.ll().scale(1,0),
|
||||
width=self.m2_width,
|
||||
height=self.height)
|
||||
# Drop a via to the M3 pin
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=vector(clk_pin.cx(),self.m3_pitch+self.m3_width))
|
||||
|
||||
|
||||
|
||||
def analytical_delay(self, slew, load=0.0):
|
||||
|
|
|
|||
|
|
@ -42,9 +42,9 @@ class replica_bitline(design.design):
|
|||
|
||||
#self.add_lvs_correspondence_points()
|
||||
|
||||
# Plus a pitch for the WL contacts on the RBL
|
||||
self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m1_pitch
|
||||
self.height = max(self.rbl_inst.uy(), self.dc_inst.uy())
|
||||
# Extra pitch on top and right
|
||||
self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m2_pitch
|
||||
self.height = max(self.rbl_inst.uy(), self.dc_inst.uy()) + self.m3_pitch
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
|
|
|
|||
|
|
@ -29,26 +29,31 @@ class sram_1bank(sram_base):
|
|||
# No orientation or offset
|
||||
self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
|
||||
|
||||
control_pos = vector(-self.control_logic.width - self.m3_pitch,
|
||||
# The control logic is placed such that the vertical center (between the delay/RBL and
|
||||
# the actual control logic is aligned with the vertical center of the bank (between
|
||||
# the sense amps/column mux and cell array)
|
||||
# The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
|
||||
# up to the row address DFFs.
|
||||
control_pos = vector(-self.control_logic.width - 2*self.m2_pitch,
|
||||
self.bank.bank_center.y - self.control_logic.control_logic_center.y)
|
||||
self.add_control_logic(position=control_pos)
|
||||
|
||||
# Leave room for the control routes to the left of the flops
|
||||
# The row address bits are placed above the control logic aligned on the right.
|
||||
row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width,
|
||||
control_pos.y + self.control_logic.height + self.m1_pitch)
|
||||
self.control_logic_inst.uy())
|
||||
self.add_row_addr_dff(row_addr_pos)
|
||||
|
||||
# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
|
||||
data_gap = -self.m2_pitch*(self.word_size+1)
|
||||
|
||||
# Add the column address below the bank under the control
|
||||
# Keep it aligned with the data flops
|
||||
# The column address flops are aligned with the data flops
|
||||
if self.col_addr_dff:
|
||||
col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width,
|
||||
data_gap - self.col_addr_dff.height)
|
||||
self.add_col_addr_dff(col_addr_pos)
|
||||
|
||||
# Add the data flops below the bank
|
||||
# Add the data flops below the bank to the right of the center of bank:
|
||||
# This relies on the center point of the bank:
|
||||
# decoder in upper left, bank in upper right, sensing in lower right.
|
||||
# These flops go below the sensing and leave a gap to channel route to the
|
||||
|
|
@ -104,13 +109,44 @@ class sram_1bank(sram_base):
|
|||
|
||||
def route_clk(self):
|
||||
""" Route the clock network """
|
||||
debug.warning("Clock is top-level must connect.")
|
||||
# For now, just have four clock pins for the address (x2), data, and control
|
||||
if self.col_addr_dff:
|
||||
self.copy_layout_pin(self.col_addr_dff_inst, "clk")
|
||||
self.copy_layout_pin(self.row_addr_dff_inst, "clk")
|
||||
self.copy_layout_pin(self.data_dff_inst, "clk")
|
||||
|
||||
# This is the actual input to the SRAM
|
||||
self.copy_layout_pin(self.control_logic_inst, "clk")
|
||||
|
||||
# Connect all of these clock pins to the clock in the central bus
|
||||
# This is something like a "spine" clock distribution. The two spines
|
||||
# are clk_buf and clk_buf_bar
|
||||
|
||||
bank_clk_buf_pin = self.bank_inst.get_pin("clk_buf")
|
||||
bank_clk_buf_pos = bank_clk_buf_pin.center()
|
||||
bank_clk_buf_bar_pin = self.bank_inst.get_pin("clk_buf_bar")
|
||||
bank_clk_buf_bar_pos = bank_clk_buf_bar_pin.center()
|
||||
|
||||
if self.col_addr_dff:
|
||||
dff_clk_pin = self.col_addr_dff_inst.get_pin("clk")
|
||||
dff_clk_pos = dff_clk_pin.center()
|
||||
mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y)
|
||||
self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos])
|
||||
|
||||
data_dff_clk_pin = self.data_dff_inst.get_pin("clk")
|
||||
data_dff_clk_pos = data_dff_clk_pin.center()
|
||||
mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y)
|
||||
self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos])
|
||||
|
||||
# This uses a metal2 track to the right of the control/row addr DFF
|
||||
# to route vertically.
|
||||
control_clk_buf_pin = self.control_logic_inst.get_pin("clk_buf")
|
||||
control_clk_buf_pos = control_clk_buf_pin.rc()
|
||||
row_addr_clk_pin = self.row_addr_dff_inst.get_pin("clk")
|
||||
row_addr_clk_pos = row_addr_clk_pin.rc()
|
||||
mid1_pos = vector(self.row_addr_dff_inst.rx() + self.m2_pitch,
|
||||
row_addr_clk_pos.y)
|
||||
mid2_pos = vector(mid1_pos.x,
|
||||
control_clk_buf_pos.y)
|
||||
# Note, the via to the control logic is taken care of when we route
|
||||
# the control logic to the bank
|
||||
self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, mid2_pos, control_clk_buf_pos])
|
||||
|
||||
|
||||
def route_vdd_gnd(self):
|
||||
""" Propagate all vdd/gnd pins up to this level for all modules """
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ class sram_base(design):
|
|||
""" Add the horizontal and vertical busses """
|
||||
# Vertical bus
|
||||
# The order of the control signals on the control bus:
|
||||
self.control_bus_names = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
|
||||
self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
|
||||
self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
|
||||
pitch=self.m2_pitch,
|
||||
offset=self.vertical_bus_offset,
|
||||
|
|
@ -328,8 +328,7 @@ class sram_base(design):
|
|||
temp.append("A[{0}]".format(i))
|
||||
if(self.num_banks > 1):
|
||||
temp.append("bank_sel[{0}]".format(bank_num))
|
||||
temp.extend(["s_en", "w_en", "tri_en_bar", "tri_en",
|
||||
"clk_buf_bar","clk_buf" , "vdd", "gnd"])
|
||||
temp.extend(["s_en", "w_en", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
|
||||
self.connect_inst(temp)
|
||||
|
||||
return bank_inst
|
||||
|
|
@ -347,8 +346,7 @@ class sram_base(design):
|
|||
inputs.append("ADDR[{}]".format(i+self.col_addr_size))
|
||||
outputs.append("A[{}]".format(i+self.col_addr_size))
|
||||
|
||||
# FIXME clk->clk_buf
|
||||
self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
|
||||
self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
|
||||
|
||||
|
||||
def add_col_addr_dff(self, position):
|
||||
|
|
@ -363,8 +361,7 @@ class sram_base(design):
|
|||
inputs.append("ADDR[{}]".format(i))
|
||||
outputs.append("A[{}]".format(i))
|
||||
|
||||
# FIXME clk->clk_buf
|
||||
self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
|
||||
self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
|
||||
|
||||
def add_data_dff(self, position):
|
||||
""" Add and place all data flops """
|
||||
|
|
@ -378,8 +375,7 @@ class sram_base(design):
|
|||
inputs.append("DIN[{}]".format(i))
|
||||
outputs.append("BANK_DIN[{}]".format(i))
|
||||
|
||||
# FIXME clk->clk_buf_bar
|
||||
self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
|
||||
self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
|
||||
|
||||
def add_control_logic(self, position):
|
||||
""" Add and place control logic """
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ class sram_1bank_test(openram_test):
|
|||
debug.info(1, "Single bank, eight way column mux with control logic")
|
||||
a = sram(word_size=2, num_words=128, num_banks=1, name="sram4")
|
||||
self.local_check(a, final_verification=True)
|
||||
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
|
|
|
|||
|
|
@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
|
|||
data = d.analyze(probe_address, probe_data, slews, loads)
|
||||
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
golden_data = {'delay_hl': [2.5614],
|
||||
'delay_lh': [0.22929839999999999],
|
||||
'leakage_power': 0.0020326,
|
||||
golden_data = {'delay_hl': [2.5829000000000004],
|
||||
'delay_lh': [0.2255964],
|
||||
'leakage_power': 0.0019498999999999996,
|
||||
'min_period': 4.844,
|
||||
'read0_power': [0.0497676],
|
||||
'read1_power': [0.0463576],
|
||||
'slew_hl': [0.1119293],
|
||||
'slew_lh': [0.0237043],
|
||||
'write0_power': [0.0494321],
|
||||
'write1_power': [0.0457268]}
|
||||
'read0_power': [0.055371399999999994],
|
||||
'read1_power': [0.0520225],
|
||||
'slew_hl': [0.0794261],
|
||||
'slew_lh': [0.0236264],
|
||||
'write0_power': [0.06545659999999999],
|
||||
'write1_power': [0.057846299999999996]}
|
||||
elif OPTS.tech_name == "scn3me_subm":
|
||||
golden_data = {'delay_hl': [6.0052],
|
||||
'delay_lh': [2.2886],
|
||||
'leakage_power': 0.025629199999999998,
|
||||
'min_period': 9.375,
|
||||
'read0_power': [8.8721],
|
||||
'read1_power': [8.3179],
|
||||
'slew_hl': [1.0746],
|
||||
'slew_lh': [0.413426],
|
||||
'write0_power': [8.6601],
|
||||
'write1_power': [8.0397]}
|
||||
golden_data = {'delay_hl': [4.0249],
|
||||
'delay_lh': [2.2611],
|
||||
'leakage_power': 0.0257389,
|
||||
'min_period': 4.688,
|
||||
'read0_power': [24.9279],
|
||||
'read1_power': [24.0219],
|
||||
'slew_hl': [0.8500753999999999],
|
||||
'slew_lh': [0.4122653],
|
||||
'write0_power': [28.197600000000005],
|
||||
'write1_power': [25.685]}
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
# Check if no too many or too few results
|
||||
|
|
|
|||
|
|
@ -50,27 +50,27 @@ class timing_sram_test(openram_test):
|
|||
data = d.analyze(probe_address, probe_data, slews, loads)
|
||||
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
golden_data = {'delay_hl': [2.562671],
|
||||
'delay_lh': [0.2320771],
|
||||
'leakage_power': 0.00102373,
|
||||
golden_data = {'delay_hl': [2.584251],
|
||||
'delay_lh': [0.22870469999999998],
|
||||
'leakage_power': 0.0009567935,
|
||||
'min_period': 4.844,
|
||||
'read0_power': [0.047404110000000006],
|
||||
'read1_power': [0.0438884],
|
||||
'slew_hl': [0.1140206],
|
||||
'slew_lh': [0.02492785],
|
||||
'write0_power': [0.04765188],
|
||||
'write1_power': [0.04434999]}
|
||||
'read0_power': [0.0547588],
|
||||
'read1_power': [0.051159970000000006],
|
||||
'slew_hl': [0.08164099999999999],
|
||||
'slew_lh': [0.025474979999999998],
|
||||
'write0_power': [0.06513271999999999],
|
||||
'write1_power': [0.058057000000000004]}
|
||||
elif OPTS.tech_name == "scn3me_subm":
|
||||
golden_data = {'delay_hl': [11.69536],
|
||||
'delay_lh': [1.260921],
|
||||
'leakage_power': 0.00039469710000000004,
|
||||
'min_period': 20.0,
|
||||
'read0_power': [4.40238],
|
||||
'read1_power': [4.126633],
|
||||
'slew_hl': [1.259555],
|
||||
'slew_lh': [0.9150649],
|
||||
'write0_power': [4.988347],
|
||||
'write1_power': [4.473887]}
|
||||
golden_data = {'delay_hl': [4.221382999999999],
|
||||
'delay_lh': [2.6459520000000003],
|
||||
'leakage_power': 0.0013865260000000001,
|
||||
'min_period': 4.688,
|
||||
'read0_power': [26.699669999999998],
|
||||
'read1_power': [26.13123],
|
||||
'slew_hl': [0.9821776000000001],
|
||||
'slew_lh': [1.5791520000000001],
|
||||
'write0_power': [30.71939],
|
||||
'write1_power': [27.44753]}
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
|||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSb", "WEb", "OEb"]
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
|||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSb", "WEb", "OEb"]
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
|
|
|
|||
Loading…
Reference in New Issue