mirror of https://github.com/VLSIDA/OpenRAM.git
Add create_bus and connect_bus api
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@ -537,7 +537,7 @@ class layout(lef.lef):
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""" Create a horizontal bus. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False)
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def create_horiontal_bus(self, layer, pitch, offset, names, length):
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def create_horizontal_bus(self, layer, pitch, offset, names, length):
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""" Create a horizontal bus. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False)
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@ -546,6 +546,8 @@ class layout(lef.lef):
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"""
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Create a horizontal or vertical bus. It can be either just rectangles, or actual
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layout pins. It returns an map of line center line positions indexed by name.
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The other coordinate is a 0 since the bus provides a range.
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TODO: combine with channel router.
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"""
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# half minwidth so we can return the center line offsets
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@ -564,7 +566,8 @@ class layout(lef.lef):
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self.add_rect(layer=layer,
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offset=line_offset,
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height=length)
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line_positions[names[i]]=line_offset+vector(half_minwidth,0)
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# Make this the center of the rail
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line_positions[names[i]]=line_offset+vector(half_minwidth,0.5*length)
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else:
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for i in range(len(names)):
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line_offset = offset + vector(0,i*pitch + half_minwidth)
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@ -577,10 +580,60 @@ class layout(lef.lef):
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self.add_rect(layer=layer,
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offset=line_offset,
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width=length)
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line_positions[names[i]]=line_offset+vector(0,half_minwidth)
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# Make this the center of the rail
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line_positions[names[i]]=line_offset+vector(0.5*length,half_minwidth)
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return line_positions
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def connect_horizontal_bus(self, mapping, inst, bus_offsets,
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layer_stack=("metal1","via1","metal2")):
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""" Horizontal version of connect_bus. """
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self.connect_bus(mapping, inst, bus_offsets, layer_stack, True)
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def connect_vertical_bus(self, mapping, inst, bus_offsets,
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layer_stack=("metal1","via1","metal2")):
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""" Vertical version of connect_bus. """
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self.connect_bus(mapping, inst, bus_offsets, layer_stack, False)
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def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal):
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"""
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Connect a mapping of pin -> name for a bus. This could be
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replaced with a channel router in the future.
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"""
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(horizontal_layer, via_layer, vertical_layer)=layer_stack
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if horizontal:
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route_layer = vertical_layer
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else:
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route_layer = horizontal_layer
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for (pin_name, bus_name) in mapping:
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pin = inst.get_pin(pin_name)
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pin_pos = pin.center()
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bus_pos = bus_offsets[bus_name]
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if horizontal:
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# up/down then left/right
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mid_pos = vector(pin_pos.x, bus_pos.y)
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else:
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# left/right then up/down
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mid_pos = vector(bus_pos.x, pin_pos.y)
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self.add_wire(layer_stack,[bus_pos, mid_pos, pin_pos])
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# Connect to the pin on the instances with a via if it is
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# not on the right layer
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if pin.layer != route_layer:
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self.add_via_center(layers=layer_stack,
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offset=pin_pos,
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rotate=90)
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# We only need a via if they happened to align perfectly
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# so the add_wire didn't add a via
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if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x):
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self.add_via_center(layers=layer_stack,
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offset=bus_pos,
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rotate=90)
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def add_enclosure(self, insts, layer="nwell"):
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""" Add a layer that surrounds the given instances. Useful
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for creating wells, for example. Doesn't check for minimum widths or
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