Add wells to fix DRC errors in SCMOS library cells.

compiler/tests/01_library_drc_test.py

@@ -26,7 +26,7 @@ class library_drc_test(unittest.TestCase):
                 drc_errors += 1
                 debug.error("Missing GDS file: {}".format(gds_name))
             drc_errors += verify.run_drc(name, gds_name)
-
+            self.assertEqual(drc_errors, 0)
         # fails if there are any DRC errors on any cells
         self.assertEqual(drc_errors, 0)
         globals.end_openram()

technology/scn3me_subm/mag_lib/cell_6t.mag

@@ -1,6 +1,10 @@
 magic
 tech scmos
-timestamp 1425318832
+timestamp 1516665972
+<< nwell >>
+rect -5 31 42 52
+<< pwell >>
+rect -5 -6 42 31
 << ntransistor >>
 rect 7 12 9 20
 rect 29 12 31 20

technology/scn3me_subm/mag_lib/ms_flop.mag

@@ -1,6 +1,10 @@
 magic
 tech scmos
-timestamp 1424105514
+timestamp 1516666526
+<< nwell >>
+rect -2 0 18 200
+<< pwell >>
+rect 18 0 40 200
 << ntransistor >>
 rect 24 178 27 180
 rect 24 162 27 164

technology/scn3me_subm/mag_lib/replica_cell_6t.mag

@@ -1,6 +1,10 @@
 magic
 tech scmos
-timestamp 1424371826
+timestamp 1516666672
+<< nwell >>
+rect -4 31 42 53
+<< pwell >>
+rect -4 -6 42 31
 << ntransistor >>
 rect 7 12 9 20
 rect 29 12 31 20

technology/scn3me_subm/mag_lib/sense_amp.mag

@@ -1,6 +1,10 @@
 magic
 tech scmos
-timestamp 1424193153
+timestamp 1516667220
+<< nwell >>
+rect 0 0 40 83
+<< pwell >>
+rect 0 83 40 152
 << ntransistor >>
 rect 21 115 23 128
 rect 12 89 14 102

technology/scn3me_subm/mag_lib/tri_gate.mag

@@ -1,6 +1,10 @@
 magic
 tech scmos
-timestamp 1428529544
+timestamp 1516666759
+<< nwell >>
+rect -2 45 38 73
+<< pwell >>
+rect -2 0 38 45
 << ntransistor >>
 rect 9 27 11 31
 rect 17 27 19 31

technology/scn3me_subm/mag_lib/write_driver.mag

@@ -1,6 +1,12 @@
 magic
 tech scmos
-timestamp 1424105890
+timestamp 1516667113
+<< nwell >>
+rect -3 100 37 137
+rect -3 -1 37 50
+<< pwell >>
+rect -3 137 37 201
+rect -3 50 37 100
 << ntransistor >>
 rect 9 176 11 188
 rect 17 176 19 188