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Make pinvbuf have unique names for GDS compliance. 

Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
This commit is contained in:
Matt Guthaus 2018-07-26 11:40:40 -07:00
parent 00a87d57ab
commit e827c1b8c7
2 changed files with 10 additions and 6 deletions
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10
compiler/modules/control_logic.py
View File

@ -349,12 +349,12 @@ class control_logic(design.design):
# input: WE, CS output: w_en_bar
w_en_bar_offset = vector(x_off, y_off)
self.w_en_bar_inst=self.add_inst(name="nand2_w_en_bar",
mod=self.nand2,
self.w_en_bar_inst=self.add_inst(name="nand3_w_en_bar",
mod=self.nand3,
offset=w_en_bar_offset,
mirror=mirror)
self.connect_inst(["cs", "we", "w_en_bar", "vdd", "gnd"])
x_off += self.nand2.width
self.connect_inst(["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"])
x_off += self.nand3.width
# input: w_en_bar, output: pre_w_en
pre_w_en_offset = vector(x_off, y_off)
@ -460,7 +460,7 @@ class control_logic(design.design):
def route_wen(self):
wen_map = zip(["A", "B"], ["cs", "we"])
wen_map = zip(["A", "B", "C"], ["clk_buf_bar", "cs", "we"])
self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets)
# Connect the NAND3 output to the inverter

6
compiler/pgates/pinvbuf.py
View File

@ -15,6 +15,8 @@ class pinvbuf(design.design):
c = reload(__import__(OPTS.bitcell))
bitcell = getattr(c, OPTS.bitcell)
unique_id = 1
def __init__(self, driver_size=4, height=bitcell.height, name=""):
stage_effort = 4
@ -26,7 +28,9 @@ class pinvbuf(design.design):
predriver_size = max(int(driver_size/(stage_effort/2)),1)
if name=="":
name = "pinvbuf_{0}_{1}".format(predriver_size, driver_size)
name = "pinvbuf_{0}_{1}_{2}".format(predriver_size, driver_size, pinvbuf.unique_id)
pinvbuf.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))