mirror of https://github.com/VLSIDA/OpenRAM.git
Edited delay measures to handle multiple readwrite ports. This commit is not well tested.
This commit is contained in:
Hunter Nichols
parent
fa8434e5f0
commit
ffe59bdf51
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@ -207,27 +207,19 @@ class delay():
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self.sf.close()
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def write_delay_measures(self):
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def write_delay_measures_one_port(self, port):
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"""
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Write the measure statements to quantify the delay and power results.
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Write the measure statements to quantify the delay and power results for one port.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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# what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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# Trigger on the clk of the appropriate cycle
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trig_name = "clk"
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targ_port = 0
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#Target name should be an input to the function or a member variable. That way, the ports can be singled out for testing
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targ_name = "{0}".format("DOUT_RWP{0}[{1}]".format(targ_port,self.probe_data))
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targ_name = "{0}".format("DOUT_{0}[{1}]".format(port,self.probe_data))
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trig_val = targ_val = 0.5 * self.vdd_voltage
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# Delay the target to measure after the negative edge
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self.stim.gen_meas_delay(meas_name="DELAY_HL",
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self.stim.gen_meas_delay(meas_name="DELAY_HL_{0}".format(port),
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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@ -237,7 +229,7 @@ class delay():
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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self.stim.gen_meas_delay(meas_name="DELAY_LH",
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self.stim.gen_meas_delay(meas_name="DELAY_LH_{0}".format(port),
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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@ -247,7 +239,7 @@ class delay():
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle])
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self.stim.gen_meas_delay(meas_name="SLEW_HL",
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self.stim.gen_meas_delay(meas_name="SLEW_HL_{0}".format(port),
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.9*self.vdd_voltage,
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@ -257,7 +249,7 @@ class delay():
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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self.stim.gen_meas_delay(meas_name="SLEW_LH",
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self.stim.gen_meas_delay(meas_name="SLEW_LH_{0}".format(port),
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.1*self.vdd_voltage,
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@ -270,29 +262,47 @@ class delay():
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# add measure statements for power
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t_initial = self.cycle_times[self.write0_cycle]
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t_final = self.cycle_times[self.write0_cycle+1]
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self.stim.gen_meas_power(meas_name="WRITE0_POWER",
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self.stim.gen_meas_power(meas_name="WRITE0_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.write1_cycle]
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t_final = self.cycle_times[self.write1_cycle+1]
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self.stim.gen_meas_power(meas_name="WRITE1_POWER",
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self.stim.gen_meas_power(meas_name="WRITE1_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read0_cycle]
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t_final = self.cycle_times[self.read0_cycle+1]
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self.stim.gen_meas_power(meas_name="READ0_POWER",
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self.stim.gen_meas_power(meas_name="READ0_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read1_cycle]
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t_final = self.cycle_times[self.read1_cycle+1]
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self.stim.gen_meas_power(meas_name="READ1_POWER",
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self.stim.gen_meas_power(meas_name="READ1_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the delay and power results for all ports.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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# what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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for readwrite_port in self.readwrite_ports:
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self.write_delay_measures_one_port(readwrite_port)
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# for read_port in self.read_ports:
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# self.write_delay_measures_one_port(read_ports)
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# for write_port in self.write_ports:
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# self.write_delay_measures_one_port(write_ports)
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def write_power_measures(self):
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"""
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Write the measure statements to quantify the leakage power only.
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@ -351,37 +361,49 @@ class delay():
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works on the trimmed netlist by default, so powers do not
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include leakage of all cells.
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"""
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result = {}
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim()
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delay_hl = parse_spice_list("timing", "delay_hl")
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delay_lh = parse_spice_list("timing", "delay_lh")
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slew_hl = parse_spice_list("timing", "slew_hl")
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slew_lh = parse_spice_list("timing", "slew_lh")
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delays = (delay_hl, delay_lh, slew_hl, slew_lh)
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#Only readwrite ports for now. Other to be added later.
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for readwrite_port in self.readwrite_ports:
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readwrite_port = readwrite_port.lower()
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delay_hl = parse_spice_list("timing", "delay_hl_{0}".format(readwrite_port))
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delay_lh = parse_spice_list("timing", "delay_lh_{0}".format(readwrite_port))
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slew_hl = parse_spice_list("timing", "slew_hl_{0}".format(readwrite_port))
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slew_lh = parse_spice_list("timing", "slew_lh_{0}".format(readwrite_port))
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delays = (delay_hl, delay_lh, slew_hl, slew_lh)
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read0_power=parse_spice_list("timing", "read0_power")
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write0_power=parse_spice_list("timing", "write0_power")
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read1_power=parse_spice_list("timing", "read1_power")
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write1_power=parse_spice_list("timing", "write1_power")
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read0_power=parse_spice_list("timing", "read0_power_{0}".format(readwrite_port))
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write0_power=parse_spice_list("timing", "write0_power_{0}".format(readwrite_port))
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read1_power=parse_spice_list("timing", "read1_power_{0}".format(readwrite_port))
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write1_power=parse_spice_list("timing", "write1_power_{0}".format(readwrite_port))
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if not self.check_valid_delays(delays):
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return (False,{})
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if not self.check_valid_delays(delays):
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return (False,{})
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# For debug, you sometimes want to inspect each simulation.
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#key=raw_input("press return to continue")
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# Scale results to ns and mw, respectively
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result = { "delay_hl" : delay_hl*1e9,
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#This is to be changed later. Most of the characterization relies that these names are preserved or nothing will work.
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#Therefore, changing these names would require changing names in most of delay.py functions and lib.py.
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result.update({ "delay_hl" : delay_hl*1e9,
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"delay_lh" : delay_lh*1e9,
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"slew_hl" : slew_hl*1e9,
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"slew_lh" : slew_lh*1e9,
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"read0_power" : read0_power*1e3,
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"read1_power" : read1_power*1e3,
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"write0_power" : write0_power*1e3,
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"write1_power" : write1_power*1e3}
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"write1_power" : write1_power*1e3})
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# for read_port in self.read_ports:
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# self.write_delay_measures_one_port(read_ports)
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# for write_port in self.write_ports:
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# self.write_delay_measures_one_port(write_ports)
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# For debug, you sometimes want to inspect each simulation.
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#key=raw_input("press return to continue")
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# Scale results to ns and mw, respectively
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# The delay is from the negative edge for our SRAM
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return (True,result)
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@ -484,45 +506,50 @@ class delay():
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim()
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delay_hl = parse_spice_list("timing", "delay_hl")
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delay_lh = parse_spice_list("timing", "delay_lh")
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slew_hl = parse_spice_list("timing", "slew_hl")
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slew_lh = parse_spice_list("timing", "slew_lh")
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# if it failed or the read was longer than a period
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if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
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debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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delay_hl *= 1e9
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delay_lh *= 1e9
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slew_hl *= 1e9
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slew_lh *= 1e9
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if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
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debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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else:
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if not relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh))
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#Only readwrite ports for now. Other to be added later.
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for readwrite_port in self.readwrite_ports:
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readwrite_port = readwrite_port.lower()
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delay_hl = parse_spice_list("timing", "delay_hl_{0}".format(readwrite_port))
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delay_lh = parse_spice_list("timing", "delay_lh_{0}".format(readwrite_port))
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slew_hl = parse_spice_list("timing", "slew_hl_{0}".format(readwrite_port))
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slew_lh = parse_spice_list("timing", "slew_lh_{0}".format(readwrite_port))
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# if it failed or the read was longer than a period
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if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
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debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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elif not relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl))
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delay_hl *= 1e9
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delay_lh *= 1e9
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slew_hl *= 1e9
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slew_lh *= 1e9
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if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
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debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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else:
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if not relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh))
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return False
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elif not relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl))
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return False
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#key=raw_input("press return to continue")
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#key=raw_input("press return to continue")
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debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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debug.info(2,"Successful period {0}, Port {5}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh,
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readwrite_port))
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return True
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def set_probe(self,probe_address, probe_data):
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