mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed format test. It was not performing checks due to moving of OPENRAM_HOME. Fixed some tabs and print statements.
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9f6bd6c9d3
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bd7958be28
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@ -385,16 +385,16 @@ class delay():
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return None
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debug.info(1, "Min Period for high_to_low transistion: {0}n with a delay of {1}".format(min_period0, delay0))
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read_power=ch.convert_to_float(ch.parse_output("timing", "power_read"))
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write_power=ch.convert_to_float(ch.parse_output("timing", "power_write"))
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write_power=ch.convert_to_float(ch.parse_output("timing", "power_write"))
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data = {"min_period1": min_period1, # period in ns
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data = {"min_period1": min_period1, # period in ns
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"delay1": delay1, # delay in s
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"min_period0": min_period0,
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"delay0": delay0,
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"read_power": read_power,
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"write_power": write_power
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}
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return data
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return data
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def obtain_cycle_times(self, slow_period, fast_period):
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@ -149,7 +149,7 @@ class lib:
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CONS2 = ["INPUT_BY_TRANS_FOR_CLOCK" , "INPUT_BY_TRANS_FOR_SIGNAL"]
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for i in CONS2:
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self.lib.write(" power_lut_template({0})".format(i))
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self.lib.write("{\n")
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self.lib.write("{\n")
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self.lib.write(" variable_1 : input_transition_time;\n")
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self.lib.write(" index_1 (\"0.5\");\n")
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self.lib.write(" }\n\n")
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@ -216,30 +216,30 @@ class lib:
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" clocked_on : clk; \n")
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self.lib.write(" }\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"OEb & !clk\"; \n")
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self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["write_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["write_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"OEb & !clk\"; \n")
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self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["write_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["write_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.write_timing(times)
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self.write_timing(times)
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self.lib.write(" memory_read(){ \n")
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" }\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!OEb & !clk\"; \n")
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self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["read_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["read_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!OEb & !clk\"; \n")
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self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["read_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
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self.lib.write(" values(\"{0}\");\n".format(data["read_power"]* 1e3))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" timing_type : rising_edge; \n")
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@ -295,8 +295,8 @@ class lib:
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self.lib.write(" clock : true;\n")
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self.lib.write(" direction : input; \n")
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
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min_pulse_width = (ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"]))/2.0
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min_period = ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"])
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min_pulse_width = (ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"]))/2.0
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min_period = ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"])
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type :\"min_pulse_width\"; \n")
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self.lib.write(" related_pin : clk; \n")
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@ -16,7 +16,7 @@ class code_format_test(unittest.TestCase):
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"Run a test to check for tabs instead of spaces in the all source files."
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def runTest(self):
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source_code_dir = os.environ["OPENRAM_HOME"] + "/compiler"
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source_code_dir = os.environ["OPENRAM_HOME"]
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source_codes = setup_files(source_code_dir)
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errors = 0
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@ -32,7 +32,9 @@ class code_format_test(unittest.TestCase):
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continue
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if re.search("debug.py$", code):
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continue
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if re.search("header.py$", code):
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if re.search("testutils.py$", code):
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continue
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if re.search("globals.py$", code):
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continue
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if re.search("openram.py$", code):
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continue
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