changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit

compiler/modules/bitcell.py

@@ -11,7 +11,7 @@ class bitcell(design.design):
     library.
     """
 
-    pin_names = ["BL", "BR", "WL", "vdd", "gnd"]
+    pin_names = ["bl", "br", "wl", "vdd", "gnd"]
     (width,height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"], layer["boundary"])
 
@@ -37,7 +37,7 @@ class bitcell(design.design):
    
  
     def list_bitcell_pins(self, col, row):
-        # Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array
+        """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
         bitcell_pins = ["bl[{0}]".format(col),
                         "br[{0}]".format(col),
                         "wl[{0}]".format(row),
@@ -47,44 +47,44 @@ class bitcell(design.design):
         
     
     def list_row_pins(self):
-        # Creates a list of row pins
-        row_pins = ["WL"]    
+        """ Creates a list of all row pins (except for gnd and vdd) """
+        row_pins = ["wl"]    
         return row_pins
     
     def list_read_row_pins(self):
-        # Creates a list of row pins
-        row_pins = ["WL"]    
+        """ Creates a list of row pins associated with read ports """
+        row_pins = ["wl"]    
         return row_pins
         
     def list_write_row_pins(self):
-        # Creates a list of row pins
-        row_pins = ["WL"]    
+        """ Creates a list of row pins associated with write ports """
+        row_pins = ["wl"]    
         return row_pins
     
     
     def list_column_pins(self):
-        # Creates a list of column pins
-        column_pins = ["BL", "BR"]
+        """ Creates a list of all column pins (except for gnd and vdd) """
+        column_pins = ["bl", "br"]
         return column_pins
         
     def list_read_column_pins(self):
-        # Creates a list of column pins
-        column_pins = ["BL"]
+        """ Creates a list of column pins associated with read ports """
+        column_pins = ["bl"]
         return column_pins
     
     def list_read_bar_column_pins(self):
-        # Creates a list of column pins
-        column_pins = ["BR"]
+        """ Creates a list of column pins associated with read_bar ports """
+        column_pins = ["br"]
         return column_pins
         
     def list_write_column_pins(self):
-        # Creates a list of column pins
-        column_pins = ["BL"]
+        """ Creates a list of column pins associated with write ports """
+        column_pins = ["bl"]
         return column_pins
     
     def list_write_bar_column_pins(self):
-        # Creates a list of column pins
-        column_pins = ["BR"]
+        """ Creates a list of column pins asscociated with write_bar ports"""
+        column_pins = ["br"]
         return column_pins
     
     def analytical_power(self, proc, vdd, temp, load):

compiler/pgates/precharge.py

@@ -81,12 +81,12 @@ class precharge(pgate.pgate):
         """Adds both the upper_pmos and lower_pmos to the module"""
         # adds the lower pmos to layout
         #base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
-        self.lower_pmos_position = vector(self.bitcell.get_pin("BL").lx(),
+        self.lower_pmos_position = vector(self.bitcell.get_pin("bl").lx(),
                                           self.pmos.active_offset.y)
         self.lower_pmos_inst=self.add_inst(name="lower_pmos",
                                            mod=self.pmos,
                                            offset=self.lower_pmos_position)
-        self.connect_inst(["bl", "en", "BR", "vdd"])
+        self.connect_inst(["bl", "en", "br", "vdd"])
 
         # adds the upper pmos(s) to layout
         ydiff = self.pmos.height + 2*self.m1_space + contact.poly.width
@@ -158,7 +158,7 @@ class precharge(pgate.pgate):
     def add_bitlines(self):
         """Adds both bit-line and bit-line-bar to the module"""
         # adds the BL on metal 2
-        offset = vector(self.bitcell.get_pin("BL").cx(),0) - vector(0.5 * self.m2_width,0)
+        offset = vector(self.bitcell.get_pin("bl").cx(),0) - vector(0.5 * self.m2_width,0)
         self.add_layout_pin(text="bl",
                             layer="metal2",
                             offset=offset,
@@ -166,7 +166,7 @@ class precharge(pgate.pgate):
                             height=self.height)
 
         # adds the BR on metal 2
-        offset = vector(self.bitcell.get_pin("BR").cx(),0) - vector(0.5 * self.m2_width,0)
+        offset = vector(self.bitcell.get_pin("br").cx(),0) - vector(0.5 * self.m2_width,0)
         self.add_layout_pin(text="br",
                             layer="metal2",
                             offset=offset,

compiler/pgates/single_level_column_mux.py

@@ -39,8 +39,8 @@ class single_level_column_mux(design.design):
     def add_bitline_pins(self):
         """ Add the top and bottom pins to this cell """
 
-        bl_pos = vector(self.bitcell.get_pin("BL").lx(), 0)
-        br_pos = vector(self.bitcell.get_pin("BR").lx(), 0)
+        bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0)
+        br_pos = vector(self.bitcell.get_pin("br").lx(), 0)
 
         # bl and br
         self.add_layout_pin(text="bl",